Patents by Inventor Stefan Eckart

Stefan Eckart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200014938
    Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Inventor: Stefan Eckart
  • Patent number: 10462473
    Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 29, 2019
    Assignee: ATI Technologies ULC
    Inventor: Stefan Eckart
  • Patent number: 9984504
    Abstract: A system and method are provided for improving video encoding using content information. A three-dimensional (3D) modeling system produces an encoded video stream. The system includes a content engine, a renderer, and a video encoder. The renderer receives 3D model information from the content engine relating and to produces corresponding two-dimensional (2D) images. The video encoder receives the 2D images and produce a corresponding encoded video stream. The video encoder receives content information from the content engine, transforms the content information into encoder control information, and controls the video encoder using the encoder control information.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: May 29, 2018
    Assignee: Nvidia Corporation
    Inventors: Hassane S. Azar, Stefan Eckart, Dawid Pajak, Bryan Dudash, Swagat Mohapatra
  • Patent number: 9918098
    Abstract: In the claimed approach, a high efficiency video coding codec optimizes the memory resources used during motion vector (MV) prediction. As the codec processes block of pixels, known as coding units (CUs), the codec performs read and write operations on a fixed-sized neighbor union buffer representing the MVs associated with processed CUs. In operation, for each CU, the codec determines the indices at which proximally-located “neighbor” MVs are stored within the neighbor union buffer. The codec then uses these neighbor MVs to compute new MVs. Subsequently, the codec deterministically updates the neighbor union buffer—replacing irrelevant MVs with those new MVs that are useful for computing the MVs of unprocessed CUs. By contrast, many conventional codecs not only redundantly store MVs, but also retain irrelevant MVs. Consequently, the codec reduces memory usage and memory operations compared to conventional codecs, thereby decreasing power consumption and improving codec efficiency.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: March 13, 2018
    Assignee: NVIDIA Corporation
    Inventors: Stefan Eckart, Yu Xinyang
  • Patent number: 9483845
    Abstract: A video frame compression system includes a rendering engine that provides a current video frame and current additional rendering information. Additionally, the video frame compression system includes a warping engine that generates a warped video frame, wherein the warped video frame is a transformation of a previous video frame that is based on the current additional rendering information. Further, the video frame compression system includes a video encoder that compresses the current video frame by using the warped video frame as a reference frame and separately compresses the current additional rendering information. Still further, the video frame compression system includes a packetizer that provides main and auxiliary data streams corresponding to the compressed current video frame and the compressed current additional rendering information, respectively. A video frame decompression system and methods of video frame compression and decompression are also provided.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: November 1, 2016
    Assignee: Nvidia Corporation
    Inventors: Hassane S Azar, Dawid Pajak, Stefan Eckart, Swagat Mohapatra
  • Patent number: 9414078
    Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: August 9, 2016
    Assignee: ATI Technologies ULC
    Inventor: Stefan Eckart
  • Publication number: 20160205402
    Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.
    Type: Application
    Filed: March 18, 2016
    Publication date: July 14, 2016
    Inventor: Stefan Eckart
  • Publication number: 20150208075
    Abstract: In one embodiment of the present invention, a high efficiency video coding codec optimizes the memory resources used during motion vector (MV) prediction. As the codec processes block of pixels, known as coding units (CUs), the codec performs read and write operations on a fixed-sized neighbor union buffer representing the MVs associated with processed CUs. In operation, for each CU, the codec determines the indices at which proximally-located “neighbor” MVs are stored within the neighbor union buffer. The codec then uses these neighbor MVs to compute new MVs. Subsequently, the codec deterministically updates the neighbor union buffer—replacing irrelevant MVs with those new MVs that are useful for computing the MVs of unprocessed CUs. By contrast, many conventional codecs not only redundantly store MVs, but also retain irrelevant MVs. Consequently, the codec reduces memory usage and memory operations compared to conventional codecs, thereby decreasing power consumption and improving codec efficiency.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Stefan ECKART, Yu XINYANG
  • Publication number: 20150195521
    Abstract: The present invention facilitates efficient and effective encoding and motion detection. A system and method can include: receiving graphics frame information; performing a motion vector analysis including candidate selection utilizing motion vectors that processing has previously been initiated for; and performing an encoding utilizing results of the motion vector analysis. A candidate motion vector is selected based upon balancing of performance and accuracy. The candidate motion vector can be associated with a macro-block that is spatially and temporally close to the left in the same row as the current macro-block. In one exemplary implementation, the candidate motion vector can be within 1 to 8 macro-blocks to the left of the current macro-block. A motion vector candidate selection process for a current macro-block can be performed in which a motion vector associated with another macro-block that has completed motion vector analysis is included as a candidate for the current macro-block.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Zenjun HU, Jianjun CHEN, Stefan ECKART
  • Publication number: 20140321757
    Abstract: A video frame compression system includes a rendering engine that provides a current video frame and current additional rendering information. Additionally, the video frame compression system includes a warping engine that generates a warped video frame, wherein the warped video frame is a transformation of a previous video frame that is based on the current additional rendering information. Further, the video frame compression system includes a video encoder that compresses the current video frame by using the warped video frame as a reference frame and separately compresses the current additional rendering information. Still further, the video frame compression system includes a packetizer that provides main and auxiliary data streams corresponding to the compressed current video frame and the compressed current additional rendering information, respectively. A video frame decompression system and methods of video frame compression and decompression are also provided.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Applicant: Nvidia Corporation
    Inventors: Hassane S Azar, Dawid Pajak, Stefan Eckart, Swagat Mohapatra
  • Publication number: 20140092209
    Abstract: A system and method are provided for improving video encoding using content information. A three-dimensional (3D) modeling system produces an encoded video stream. The system includes a content engine, a renderer, and a video encoder. The renderer receives 3D model information from the content engine relating and to produces corresponding two-dimensional (2D) images. The video encoder receives the 2D images and produce a corresponding encoded video stream. The video encoder receives content information from the content engine, transforms the content information into encoder control information, and controls the video encoder using the encoder control information.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Hassane S. Azar, Stefan Eckart, Dawid Pajak, Bryan Dudash, Swagat Mohapatra
  • Patent number: 8588305
    Abstract: The present invention provides an apparatus for interpolation which is able to process input data with multiple video standards without sacrificing chip area. The interpolation unit comprises: a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit. The present invention also provides a motion compensation unit and a decoder for processing multiple video standards.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: November 19, 2013
    Assignee: Nvidia Corporation
    Inventors: Yong Peng, Zheng Wei Jiang, Frans Sijstermans, Stefan Eckart
  • Patent number: 8190668
    Abstract: An Inverse Hadamard Transform (IHT) converter and system includes a first group of registers for receiving coefficients inputted to the IHT converter; a first adder for adding selected the coefficients stored in the first group of registers; a second group of registers for receiving results from the first adder; and a second adder for adding selected the results stored in the second group of registers.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: May 29, 2012
    Assignee: NVIDIA Corporation
    Inventors: Jincheng Li, Stefan Eckart
  • Patent number: 7584475
    Abstract: A software program includes at least two performance levels. Each performance level has an associated processor utilization. Each performance level corresponds to optimization criteria, such as a quality of data processing performed by the software program. The performance level is selected to maintain processor utilization by the software program within constraints, such as a desired range of processor utilization and a minimum idle thread allocation.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: September 1, 2009
    Assignee: Nvidia Corporation
    Inventors: Michael L. Lightstone, Stefan Eckart, Hassane S. Azar
  • Publication number: 20090172061
    Abstract: The present invention provides an Inverse Hadamard Transform (IHT) converter which comprises a first group of registers for receiving coefficients inputted to the IHT converter; a first adder for adding selected the coefficients stored in the first group of registers; a second group of registers for receiving results from the first adder; and a second adder for adding selected the results stored in the second group of registers. The present invention provides an Inverse Hadamard Transform (IHT) converter system.
    Type: Application
    Filed: June 26, 2008
    Publication date: July 2, 2009
    Inventors: Jincheng Li, Stefan ECKART
  • Publication number: 20090168885
    Abstract: The present invention provides an apparatus for interpolation which is able to process input data with multiple video standards without sacrificing chip area. The interpolation unit comprises: a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit. The present invention also provides a motion compensation unit and a decoder for processing multiple video standards.
    Type: Application
    Filed: June 20, 2008
    Publication date: July 2, 2009
    Inventors: Yong Peng, Zheng Wei Jiang, Frans Sijstermans, Stefan Eckart
  • Patent number: 7535959
    Abstract: A video encoder includes a programmable rate controller. In one embodiment, the programmable rate controller includes a variable bit rate controller, a constant bit rate controller, and an arbitration logic for selecting one of the two outputs. An embodiment of a variable bit rate controller tracks long-term changes to average bit rate. An embodiment of a constant bit rate controller classifies macroblock types, determines a statistical indicator of complexity for each macroblock type, and generates a target bit rate based on estimated complexity.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: May 19, 2009
    Assignee: NVIDIA Corporation
    Inventors: Michael L. Lightstone, Stefan Eckart
  • Patent number: 7277581
    Abstract: The invention provide methods and code for better detecting 3:2 pulldown or other video formats. In one respect, embodiments of the invention improve the way in which fields of video data are compared. In another respect, embodiments of the invention provide pattern matching techniques and code for processing the field difference data.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: October 2, 2007
    Assignee: NVIDIA Corporation
    Inventors: Michael L. Lightstone, Stefan Eckart
  • Patent number: 7277483
    Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: October 2, 2007
    Assignee: ATI International SRL
    Inventor: Stefan Eckart
  • Publication number: 20070147512
    Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.
    Type: Application
    Filed: March 2, 2007
    Publication date: June 28, 2007
    Applicant: ATI International SRL
    Inventor: Stefan Eckart