Abstract: Embodiments of the invention relate to a process for producing a III-N bulk crystal, wherein III denotes at least one element selected from group III of the periodic system, selected from Al, Ga and In, wherein the III-N bulk crystal is grown by vapor phase epitaxy on a substrate, and wherein the growth rate is measured in real-time. By actively measuring and controlling the growth rate in situ, i.e. during the epitaxial growth, the actual growth rate can be maintained essentially constant. In this manner, III-N bulk crystals and individualized III-N single crystal substrates separated therefrom, which respectively have excellent crystal quality both in the growth direction and in the growth plane perpendicular thereto, can be obtained.

Abstract: A device for heat treating (annealing) a III-V semiconductor wafer comprises at least one wafer support unit which is dimensioned such that a cover provided above the wafer surface is either spaced without any distance or with a distance of maximally about 2 mm to the wafer surface. A process for heat treating III-V semiconductor wafers having diameters larger than 100 mm and a dislocation density below 1×104 cm?2 is carried out in the device of the invention. SI GaAs wafers produced have an at least 25% increased characteristic fracture strength (Weibull distribution), an improved radial macroscopic and mesoscopic homogeneity and an improved quality of the mechano-chemically polished surface. The characteristic fracture strength is higher than 1900 MPa.

Abstract: A process and a device for producing crystalline silicon, particularly poly- or multi-crystalline silicon are described, wherein a melt of a silicon starting material is formed and the silicon melt is subsequently solidified in a directed orientation. A phase or a material is provided in gaseous, fluid or solid form above the melt in such a manner, that a concentration of a foreign atom selected from oxygen, carbon and nitrogen in the silicon melt and thus in the solidified crystalline silicon is controllable, and/or that a partial pressure of a gaseous component in a gas phase above the silicon melt is adjustable and/or controllable, the gaseous component being selected from oxygen gas, carbon gas and nitrogen gas and gaseous species containing at least one element selected from oxygen, carbon and nitrogen.

Abstract: A process is disclosed for producing a doped gallium arsenide single crystal by melting a gallium arsenide starting material and subsequently solidifying the gallium arsenide melt, wherein the gallium arsenide melt contains an excess of gallium relative to the stoichiometric composition, and wherein it is provided for a boron concentration of at least 5×1017 cm?3 in the melt or in the obtained crystal. The thus obtained crystal is characterized by a unique combination of low dislocation density, high conductivity and yet excellent, very low optic absorption, particularly in the range of the near infrared.

Abstract: A device for heat treating (annealing) a III-V semiconductor wafer comprises at least one wafer support unit which is dimensioned such that a cover provided above the wafer surface is either spaced without any distance or with a distance of maximally about 2 mm to the wafer surface. A process for heat treating III-V semiconductor wafers having diameters larger than 100 mm and a dislocation density below 1×104 cm?2 is carried out in the device of the invention. SI GaAs wafers produced have an at least 25% increased characteristic fracture strength (Weibull distribution), an improved radial macroscopic and mesoscopic homogeneity and an improved quality of the mechano-chemically polished surface. The characteristic fracture strength is higher than 1900 MPa.

Abstract: An arrangement for manufacturing a crystal of the melt of a raw material comprises: a furnace having a heating device with one or more heating elements, which are configured to generate a gradient temperature field directed along a first direction, a plurality of crucibles for receiving the melt, which are arranged within the gradient temperature field side by side, and a device for homogenizing the temperature field within a plane perpendicular to the first direction in the at least two crucibles. The arrangement further has a filling material inserted within a space between the crucibles wherein the filling shows an anisotropic heat conductivity. Additionally or alternatively, the arrangement may comprise a device for generating magnetic migration fields, both the filling material having the anisotropic heat conductivity and the device for generating magnetic migration fields being suited to compensate or prevent the formation of asymmetric phase interfaces upon freezing of the raw melt.

Abstract: A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapour phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor.

Abstract: In a process for manufacturing doped semiconductor single crystal comprises solidifying in a crucible, the amount of dopant is added into the semiconductor melt after the beginning of the crystal growth onto the seed crystal, or after at least partial solidification of the semiconductor single crystal in a conical or tapered portion of the crucible. Dopant may be partially added in advance into the crucible, with the remainder added into the semiconductor melt as described. Type III-V semiconductor single crystals or wafers having a diameter of at least about 100 mm, can be prepared having an electrical conductivity of at least about 250 Siemens/cm, and/or an electric resistivity of at most about 4×10?3 ?cm, and/or a significantly improved ratio of hall mobility to charge carrier concentration.

Abstract: In a process for manufacturing doped semiconductor single crystal comprises solidifying in a crucible, the amount of dopant is added into the semiconductor melt after the beginning of the crystal growth onto the seed crystal, or after at least partial solidification of the semiconductor single crystal in a conical or tapered portion of the crucible. Dopant may be partially added in advance into the crucible, with the remainder added into the semiconductor melt as described. Type III-V semiconductor single crystals or wafers having a diameter of at least about 100 mm, can be prepared having an electrical conductivity of at least about 250 Siemens/cm, and/or an electric resistivity of at most about 4×10?3 ?cm, and/or a significantly improved ratio of hall mobility to charge carrier concentration.

Abstract: Embodiments of the invention relate to a process for producing a III-N bulk crystal, wherein III denotes at least one element selected from group III of the periodic system, selected from Al, Ga and In, wherein the III-N bulk crystal is grown by vapor phase epitaxy on a substrate, and wherein the growth rate is measured in real-time. By actively measuring and controlling the growth rate in situ, i.e. during the epitaxial growth, the actual growth rate can be maintained essentially constant. In this manner, III-N bulk crystals and individualized III-N single crystal substrates separated therefrom, which respectively have excellent crystal quality both in the growth direction and in the growth plane perpendicular thereto, can be obtained.

Abstract: A process for producing a free-standing III-N layer, where III denotes at least one element from group III of the periodic system, selected from Al, Ga and In, comprises depositing on a Li(Al,Ga)Ox substrate, where x is in a range between 1 and 3 inclusive, at least one first III-N layer by means of molecular beam epitaxy. A thick second III-N layer is deposited on the first III-N layer by means of a hydride vapor phase epitaxy. During cooling of the structure produced in this way, the Li(Al,Ga)Ox substrate completely or largely flakes off the III-N layers, or residues can be removed if necessary, by using etching liquid, such as aqua regia. A free-standing III-N substrate being substantially free of uncontrolled impurities and having advantageous properties is provided.

Abstract: A device for heat treating (annealing) a III-V semiconductor wafer comprises at least one wafer support unit which is dimensioned such that a cover provided above the wafer surface is either spaced without any distance or with a distance of maximally about 2 mm to the wafer surface. A process for heat treating III-V semiconductor wafers having diameters larger than 100 mm and a dislocation density below 1×104 cm?2 is carried out in the device of the invention. SI GaAs wafers produced have an at least 25% increased characteristic fracture strength (Weibull distribution), an improved radial macroscopic and mesoscopic homogeneity and an improved quality of the mechano-chemically polished surface. The characteristic fracture strength is higher than 1900 MPa.

Abstract: In a process for manufacturing doped semiconductor single crystal comprises solidifying in a crucible, the amount of dopant is added into the semiconductor melt after the beginning of the crystal growth onto the seed crystal, or after at least partial solidification of the semiconductor single crystal in a conical or tapered portion of the crucible. Dopant may be partially added in advance into the crucible, with the remainder added into the semiconductor melt as described. Type III-V semiconductor single crystals or wafers having a diameter of at least about 100 mm, can be prepared having an electrical conductivity of at least about 250 Siemens/cm, and/or an electric resistivity of at most about 4×10?3 ?cm, and/or a significantly improved ratio of hall mobility to charge carrier concentration.

Abstract: There is provided a heating element and an arrangement of heating elements, respectively, for heating crucibles, in particular for LEC devices for growing semiconductor single crystals, with a tulip-shaped bottom heater (20) being built such that the heater legs of the main heater (40) positioned thereabove can barely be guided towards the bottom. Such arrangement of bottom and main heater enables multi-heater arrangements without having to interfere with a lateral insulation (18) which, thus, need not be cut out or pierced.