Abstract: A digitally programmable delay circuit is provided, which includes a control input and a plurality of delay stages coupled in series with one another to form a delay line. Each stage has a previous stage input, a previous stage output, a next stage input and a next stage output. The next stage output and the next stage input are coupled to the previous stage input and the previous stage output, respectively, of a next one of the delay stages in the delay line. The previous stage input is coupled to the next stage output. The previous stage input and the next stage input are selectively coupled to the previous stage output based on the control input.

Abstract: An apparatus comprising a plurality of flip-flops each comprising (i) a first input, (ii) a second input and (iii) an output, where (a) each of the outputs are coupled to the first input of a subsequent flip-flop to form a chain, (b) the first input of a first of the flip-flops receives a pattern signal, (c) each of the second inputs receives a respective first logic signal, and (d) each of the outputs presents a respective second logic signal in response to the signals received at the first and second inputs, a pattern generator configured to generate the pattern signal, and a checking circuit configured to generate a check signal in response to the second logic signal of a last of the flip-flops. The pattern signal and the first logic signals are generally selected to influence a behavior of the apparatus.

Abstract: A method and apparatus are provided for calibrating first and second digital-to-analog converters (DACs). The apparatus has a normal input and a test input. A first correction circuit selectively modifies either the normal input or the test input by a first gain correction value and a first offset correction value to produce a first corrected value. A second correction circuit selectively modifies either the normal input or the test input by a second gain correction value and a second offset correction value to produce a second corrected value. A first DAC operates on the first corrected output and has a first analog output. A second DAC operates on the second corrected output and has a second analog output. A calibration control circuit has first and second inputs coupled to the first and second analog outputs, respectively, and generates the first and second gain correction values and the first and second offset correction values as a function of the first and second analog outputs.

Abstract: A digital multi-phase clock generator includes a reference clock input and first and second digitally-programmable delay lines. The first and second delay lines are coupled in parallel with one another, in series with the reference clock input. Each delay line includes a delay control input. The first delay line has a plurality of phase outputs which are synchronized with the reference clock input and have different phases from one another. The generator further includes a phase detector and a delay control circuit, which are coupled with second delay line to form a phase-locked loop. The delay control circuit has a digital delay control output, which is coupled to the delay control inputs of both the first and second delay lines. The phase-locked loop adjusts delay through the first and second delay lines to lock a phase of an output of the second delay line to a phase of the reference clock input.

Abstract: A method and apparatus are provided for calibrating first and second analog-to-digital converters (ADCs). The apparatus applies a test signal to the first and second ADCs. A first correction value is applied to an output of the first ADC to produce a first corrected output. A second correction value is applied to an output of the second ADC to produce a second corrected output. The first and second corrected outputs are then compared to identify a greater one and a lesser one of the first and second corrected outputs. At least one of the first and second correction values are adjusted relative to the other until the first or second corrected output that was identified as the lesser one exceeds the other.