Abstract: A method for improving the accuracy of quiescent current estimation for integrated circuits. When used with a CMOS process, the method involves selecting transistors having a polysilicon gate length corresponding to the minimum length permitted by process design rules. For each of the selected transistors, the intersection of the width of the polysilicon gate and the active area of the transistor is calculated. The widths of all of the selected minimum length devices are summed to generate a total width dimension value. The total width dimension value is multiplied by a predetermined quiescent current per unit width conversion value to produce an estimate of the quiescent current drawn by the integrated circuit. In an alternate embodiment of the invention, the total width dimension value is multiplied by a range of predetermined quiescent/leakage current per unit width values representing a range of testing conditions and temperatures.

Abstract: According to the current invention, there is provided a system for transferring data into and out of a first-in, first-out (FIFO) data buffer. The buffer has a read pointer and a write pointer. The system comprises a comparator circuit, multiple counter blocks, and multiple flag registers. The counter blocks and flag registers are connected to a system clock to provide timing information and capacity indications to the comparator. The comparator circuit continuously monitors the multiple counter blocks, thereby tracking buffer pointer positions. The flag registers indicate relative buffer capacity and provide early indication to the system that the buffer is almost full or almost empty in appropriate conditions. The comparator circuit continuously evaluates the read and write counter blocks and the flag registers to determine the ability of the buffer to accept or transmit data.

Abstract: A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.

Abstract: Magnetic sensors are positioned adjacent a semiconductor integrated circuit under test while the circuit is subjected to selected electrical stimuli for purposes of failure analysis. The magnetic image data can be acquired from one or more selected locations about the circuit without any physical connection. By comparing the magnetic sensor information to a predetermined database of magnetic information acquired from known devices, failure modes can be identified. Conventional tester equipment can be used for providing the electrical stimuli to the device under test.

Abstract: A method of testing a semiconductor device includes generating a current waveform for the semiconductor device by measuring the response of the device to an initializing vector group and comparing the current waveform to a golden waveform to determine whether the semiconductor device is good or defective. Apparatus for testing the semiconductor device includes a vector generator providing an initialization vector group to the semiconductor device, a measurement unit for measuring a plurality of current measurements from the semiconductor device which responds to the input of the initialization vector group, a generation unit for generating a current waveform from the current measurements of the semiconductor device, and an analysis unit for comparing the current waveform to a golden waveform to determine whether the device falls outside a tolerance margin of the golden waveform.

Abstract: A method for comparing intermediate test files having different file formats used to test integrated circuitry is provided. The method initially receives intermediate test files from an ATPG tool or a manually run simulation. The ATPG tool or manually run simulation provides data in a .wgl format for testing, and is a non-simulatable format, and the ATPG tool also provides a second intermediate file comprising a file or files in a simulatable format. All files contain event data used for testing. The intermediate test files are converted to files having a common format. The invention then compares the converted files to determine mismatches between the converted files. This comparison comprises evaluating the common format files and generating a pass/fail flag based on the results of the evaluation. Mismatches between the common format are corrected if the flag indicates that the files are not identical.

Abstract: A method is provided for generating test vectors to detect bridge faults in a semiconductor device. In one version of the invention, the method includes the steps of creating a net name data structure from a structural description of the semiconductor device which includes data representing the instance names for the nets to be tested, identifying a pair of nets in the net name data structure, and generating at least one test vector for the pair of nets such that, when the vectors impress on the nets, the state of the nets of the pair will change relative to each other such that logic, coupled to the pair, produces a signal which indicates whether a bridge fault exists between the nets of the pair.

Abstract: A method is provided for operating a scan chain in a semiconductor device having a plurality of serially connected logic blocks, an output from a first logic block being coupled to an input of a first latch, the output from the first latch being coupled to the input of a second logic block, an output of the second logic block being coupled to an input of a second latch, the method comprising: detecting a test enable signal; if the test enable signal is active: detecting the output of the first latch, and setting the output of the second latch to the same state as the detected output of the first latch, independently of the state of the output of the second logic block; if the test enable signal is inactive: setting the output of the second latch responsive to the output of the second logic block.

Abstract: According to the present invention, the invention relates to a semiconductor device having an activity monitor circuit formed thereon for monitoring the switching activity of signals generated by other circuits on the device during burn-in testing. In one embodiment, the activity monitor circuit includes means for detecting a present state of a signal; means for comparing the present state with a previous state of the signal; means for determining whether the state of the signal has switched a requisite number of times in a predetermined time period; and means for displaying the results of the determination.