Abstract: To fasten a first component to a second component, a fastening clip has an integral, elongated structure with a first and a second fastening end. The first fastening end comprises an at least one-armed independent latching structure. The second fastening end is formed by a resilient clamp. The first and second latching structure act on an intermediate support structure. To connect the two components, the latching structure is latched in a component opening in a first component, and the second component is fastened between the support structure and a spring loop of the resilient clamp with the assistance of a cutout or a slot that is open on one side.

Abstract: To fasten a first component to a second component, a fastening clip has an integral, elongated structure with a first and a second fastening end. The first fastening end comprises an at least one-armed independent latching structure. The second fastening end is formed by a resilient clamp. The first and second latching structure act on an intermediate support structure. To connect the two components, the latching structure is latched in a component opening in a first component, and the second component is fastened between the support structure and a spring loop of the resilient clamp with the assistance of a cutout or a slot that is open on one side.

Abstract: A method for reducing an overlay error of structures of a layer to be patterned relative to those of a reference layer includes formation of standard measurement marks assigned to one another in the two layers for determining an overlay error and for setting up further measurement marks for determining an additional optical imaging error of the projection system at least in the current layer. The further measurement marks have a geometry adapted to the geometry of selected structures of the circuit patterns to be transferred by projection from masks onto semiconductor substrates. An imaging error affects circuit structures and further measurement marks in the same way. An alignment correction for a subsequent exposure can be calculated from the measured positional deviations between the two standard measurement marks and between the standard measurement mark and the further measurement mark of the layer currently to be patterned.

Abstract: A method, suitable to photolithographie projection, for detecting the positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer. After the transfer of at least one multiple arrangement of a first test structure into at least one resist layer above the substrate, wherein the first test structure includes a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark, the values of a first positioning error of the first circuit patterns relative to the first overlay marks and the first micropatterned alignment marks are determined for each element of the at least one multiple arrangement.

Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

Abstract: A method for reducing an overlay error of structures of a layer to be patterned relative to those of a reference layer includes formation of standard measurement marks assigned to one another in the two layers for determining an overlay error and for setting up further measurement marks for determining an additional optical imaging error of the projection system at least in the current layer. The further measurement marks have a geometry adapted to the geometry of selected structures of the circuit patterns to be transferred by projection from masks onto semiconductor substrates. An imaging error affects circuit structures and further measurement marks in the same way. An alignment correction for a subsequent exposure can be calculated from the measured positional deviations between the two standard measurement marks and between the standard measurement mark and the further measurement mark of the layer currently to be patterned.

Abstract: The invention relates to a method for detecting the positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer. After the transfer of at least one multiple arrangement of a first test structure by means of photolithographic projection into at least one resist layer above the substrate, the first test structure having a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark, the values of a first positioning error of the first circuit patterns relative to the first overlay marks and the first micropatterned alignment marks are determined for each element of the at least one multiple arrangement.

Abstract: In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconduct