Patents by Inventor Stefan HAENZSCHE

Stefan HAENZSCHE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MULTI-MODE LINE DRIVER CIRCUIT FOR THE PHYSICAL LAYER OF A NETWORK CONNECTION, PARTICULARLY OF AN ETHERNET COMMUNICATION, SUPPORTING DIFFERENT SIGNAL LEVELS FOR DIFFERENT COMMUNICATION STANDARDS
    Publication number: 20230362285
    Abstract: A multi-mode line driver circuit supporting different communication standards includes an output for the network connection, and driver elements connected in parallel to the output. Each driver element is connected to a positive and negative supply voltage, and includes a resistor, a first switch and a second switch. The resistor is connected to the output and via the first switch to the positive supply voltage and via the second switch to the negative supply voltage. The driver circuit also includes at least one coding block with an input for a digital signal to be transmitted over the network connection. The coding block provides control signals for the first switch and the second switch for connecting the resistor of each driver element to the positive supply voltage or the negative supply voltage. The digital signal of the multi-mode line driver circuit is coded according to a communication standard.
    Type: Application
    Filed: October 22, 2021
    Publication date: November 9, 2023
    Applicant: SILICONALLY GMBH
    Inventors: Franz Marcus SCHUEFFNY, Stefan HAENZSCHE, Sebastian HOEPPNER, Martin KREISSIG
  • Method and arrangement for generating a clock signal by means of a phase locked loop
    Patent number: 8994418
    Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 31, 2015
    Assignee: Technische Universitaet Dresden
    Inventors: Sebastian Hoeppner, Stefan Haenzsche
  • METHOD AND ARRANGEMENT FOR GENERATING A CLOCK SIGNAL BY MEANS OF A PHASE LOCKED LOOP
    Publication number: 20140240011
    Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 28, 2014
    Applicant: TECHNISCHE UNIVERSITAET DRESDEN
    Inventors: Sebastian HOEPPNER, Stefan HAENZSCHE