Patents by Inventor Stefan Hau-Riege

Stefan Hau-Riege has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110083661
    Abstract: A low to moderate temperature heat source comprising a high temperature energy source modified to output low to moderate temperatures wherein the high temperature energy source modified to output low to moderate temperatures is positioned between two thin pieces to form a close contact sheath. In one embodiment the high temperature energy source modified to output low to moderate temperatures is a nanolaminate multilayer foil of reactive materials that produces a heating level of less than 200° C.
    Type: Application
    Filed: December 3, 2010
    Publication date: April 14, 2011
    Inventors: J. Del Eckels, Peter J. Nunes, Randall L. Simpson, Stefan Hau-Riege, Chris Walton, J. Chance Carter, John G. Reynolds
  • Patent number: 7867441
    Abstract: A low to moderate temperature heat source comprising a high temperature energy source modified to output low to moderate temperatures wherein the high temperature energy source modified to output low to moderate temperatures is positioned between two thin pieces to form a close contact sheath. In one embodiment the high temperature energy source modified to output low to moderate temperatures is a nanolaminate multilayer foil of reactive materials that produces a heating level of less than 200° C.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: January 11, 2011
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: J. Del Eckels, Peter J. Nunes, Randall L. Simpson, Stefan Hau-Riege, Chris Walton, J. Chance Carter, John G. Reynolds
  • Patent number: 7672430
    Abstract: A system in one embodiment includes a source for directing a beam of radiation at a sample; a multilayer mirror having a face oriented at an angle of less than 90 degrees from an axis of the beam from the source, the mirror reflecting at least a portion of the radiation after the beam encounters a sample; and a pixellated detector for detecting radiation reflected by the mirror. A method in a further embodiment includes directing a beam of radiation at a sample; reflecting at least some of the radiation diffracted by the sample; not reflecting at least a majority of the radiation that is not diffracted by the sample; and detecting at least some of the reflected radiation. A method in yet another embodiment includes directing a beam of radiation at a sample; reflecting at least some of the radiation diffracted by the sample using a multilayer mirror; and detecting at least some of the reflected radiation.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: March 2, 2010
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Henry N. Chapman, Sasa Bajt, Eberhard A. Spiller, Stefan Hau-Riege, Stefano Marchesini
  • Publication number: 20090116619
    Abstract: A system in one embodiment includes a source for directing a beam of radiation at a sample; a multilayer mirror having a face oriented at an angle of less than 90 degrees from an axis of the beam from the source, the mirror reflecting at least a portion of the radiation after the beam encounters a sample; and a pixellated detector for detecting radiation reflected by the mirror. A method in a further embodiment includes directing a beam of radiation at a sample; reflecting at least some of the radiation diffracted by the sample; not reflecting at least a majority of the radiation that is not diffracted by the sample; and detecting at least some of the reflected radiation. A method in yet another embodiment includes directing a beam of radiation at a sample; reflecting at least some of the radiation diffracted by the sample using a multilayer mirror; and detecting at least some of the reflected radiation.
    Type: Application
    Filed: May 15, 2008
    Publication date: May 7, 2009
    Inventors: Henry N. Chapman, Sasa Bajt, Eberhard A. Spiller, Stefan Hau-Riege, Stefano Marchesini
  • Publication number: 20080131316
    Abstract: A low to moderate temperature heat source comprising a high temperature energy source modified to output low to moderate temperatures wherein the high temperature energy source modified to output low to moderate temperatures is positioned between two thin pieces to form a close contact sheath. In one embodiment the high temperature energy source modified to output low to moderate temperatures is a nanolaminate multilayer foil of reactive materials that produces a heating level of less than 200° C.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Inventors: J. Del Eckels, Peter J. Nunes, Randall L. Simpson, Stefan Hau-Riege, Chris Walton, J. Chance Carter, John G. Reynolds
  • Patent number: 7300871
    Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: November 27, 2007
    Assignee: Intel Corporation
    Inventors: Stefan Hau-Riege, R. Scott List
  • Patent number: 7153774
    Abstract: A method of making a semiconductor device is described. That method includes forming a copper containing layer on a substrate, and forming an alloying layer that includes an alloying element on the copper containing layer. After applying heat to cause an intermetallic layer that includes copper and the alloying element to form on the surface of the copper containing layer, a barrier layer is formed on the intermetallic layer.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Stefan Hau-Riege, Christine Hau-Riege, Wen-Yue Zheng
  • Publication number: 20060234135
    Abstract: A method for repairing mask-blank defects uses repair-zone compensation. Local disturbances are compensated over the post-defect-repair repair-zone by altering a portion of the absorber pattern on the surface of the mask blank. This enables the fabrication of defect-free (since repaired) X-ray Mo—Si multilayer mirrors. Repairing Mo—Si multilayer-film defects on mask blanks is a key for the commercial success of EUVL. It is known that particles are added to the Mo—Si multilayer film during the fabrication process. There is a large effort to reduce this contamination, but results are not sufficient, and defects continue to be a major mask yield limiter.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 19, 2006
    Inventors: Stefan Hau-Riege, Donald Sweeney, Anton Barty, Paul Mirkarimi, Daniel Stearns
  • Publication number: 20050276370
    Abstract: A system for x-ray imaging of a small sample comprising positioning a tamper so that it is operatively connected to the sample, directing short intense x-ray pulses onto the tamper and the sample, and detecting an image from the sample. The tamper delays the explosive motion of the sample during irradiation by the short intense x-ray pulses, thereby extending the time to obtain an x-ray image of the original structure of the sample.
    Type: Application
    Filed: May 17, 2005
    Publication date: December 15, 2005
    Inventors: Richard London, Abraham Szoke, Stefan Hau-Riege, Henry Chapman
  • Publication number: 20050185173
    Abstract: The invention applies techniques for image reconstruction from X-ray diffraction patterns on the three-dimensional imaging of defects in EUVL multilayer films. The reconstructed image gives information about the out-of-plane position and the diffraction strength of the defect. The positional information can be used to select the correct defect repair technique. This invention enables the fabrication of defect-free (since repaired) X-ray Mo—Si multilayer mirrors. Repairing Mo—Si multilayer-film defects on mask blanks is a key for the commercial success of EUVL. It is known that particles are added to the Mo—Si multilayer film during the fabrication process. There is a large effort to reduce this contamination, but results are not sufficient, and defects continue to be a major mask yield limiter. All suggested repair strategies need to know the out-of-plane position of the defects in the multilayer.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 25, 2005
    Inventor: Stefan Hau-Riege
  • Patent number: 6925216
    Abstract: An optical waveguide structure is formed by embedding a core material within a medium of lower refractive index, i.e. the cladding. The optical index of refraction of amorphous silicon (a-Si) and polycrystalline silicon (p-Si), in the wavelength range between about 1.2 and about 1.6 micrometers, differ by up to about 20%, with the amorphous phase having the larger index. Spatially selective laser crystallization of amorphous silicon provides a mechanism for controlling the spatial variation of the refractive index and for surrounding the amorphous regions with crystalline material. In cases where an amorphous silicon film is interposed between layers of low refractive index, for example, a structure comprised of a SiO2 substrate, a Si film and an SiO2 film, the formation of guided wave structures is particularly simple.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 2, 2005
    Assignee: The Regents of the University of California
    Inventors: Steve Vernon, Tiziana C. Bond, Steven W. Bond, Michael D. Pocha, Stefan Hau-Riege
  • Publication number: 20050095751
    Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.
    Type: Application
    Filed: November 8, 2004
    Publication date: May 5, 2005
    Inventors: Stefan Hau-Riege, R. List
  • Patent number: 6870262
    Abstract: A method is provided for forming a wafer stack. This may include providing a first wafer having a first plurality of metalized trenches on a surface of the first wafer. A second wafer may be provided having a second plurality of metalized trenches on a surface of the second wafer facing the first wafer. The first plurality of metalized trenches may be solder bonded to the second plurality of metalized trenches.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: March 22, 2005
    Assignee: Intel Corporation
    Inventors: Stefan Hau-Riege, Christine Hau-Riege
  • Patent number: 6833321
    Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: December 21, 2004
    Assignee: Intel Corporation
    Inventors: Stefan Hau-Riege, R. Scott List
  • Publication number: 20040240821
    Abstract: An optical waveguide structure is formed by embedding a core material within a medium of lower refractive index, i.e. the cladding. The optical index of refraction of amorphous silicon (a-Si) and polycrystalline silicon (p-Si), in the wavelength range between about 1.2 and about 1.6 micrometers, differ by up to about 20%, with the amorphous phase having the larger index. Spatially selective laser crystallization of amorphous silicon provides a mechanism for controlling the spatial variation of the refractive index and for surrounding the amorphous regions with crystalline material. In cases where an amorphous silicon film is interposed between layers of low refractive index, for example, a structure comprised of a SiO2 substrate, a Si film and an SiO2 film, the formation of guided wave structures is particularly simple.
    Type: Application
    Filed: September 30, 2003
    Publication date: December 2, 2004
    Applicant: The Regents of the University of California
    Inventors: Steve Vernon, Tiziana C. Bond, Steven W. Bond, Michael D. Pocha, Stefan Hau-Riege
  • Patent number: 6822473
    Abstract: Electromigration permeability is determined for a layer material within an interconnect test structure comprised of a feeder line, a test line, and a supply line. A no-flux structure is disposed between the feeder line and the test line, and the layer material is disposed between the test line and the supply line. A respective current density and length product for each of the test line and the supply line is less than a critical Blech length constant, (J*L)CRIT. A net current density and length product (J*L)NET for the test line and the supply line is greater than the (J*L)CRIT. The electromigration permeability of the layer material is determined from an electromigration lifetime of the interconnect test structure with current flowing therein.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: November 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christine Hau-Riege, Stefan Hau-Riege, Amit P. Marathe
  • Patent number: 6768323
    Abstract: For locating an extrusion from an interconnect, an extrusion monitor structure is formed to surround the interconnect and is separated from the interconnect by a dielectric material. A first via is coupled to the interconnect, and a second via is coupled to the extrusion monitor structure and separated from the first via by a via distance (Lv). The extrusion is located at an extrusion site distance (Lextrusion) from the first via and between the first and second vias to short-circuit the interconnect to the extrusion monitor structure. A resistance (Rtotal) between the first and second vias is measured, and the Lextrusion is determined from a relationship with Rtotal, Lv, and resistivities and dimensions of the interconnect and the extrusion monitor structure.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: July 27, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christine Hau-Riege, Stefan Hau-Riege
  • Patent number: 6762597
    Abstract: For determining electromigration permeability of a layer material, a test line, a feeder line, and a cathode line of an interconnect test structure are formed with current flowing from the test line through the feeder line to the cathode line. A no-flux structure is disposed between the cathode line and the feeder line, and the layer material is disposed between the feeder line and the test line. A respective current density and length product of the feeder line and the test line is respectively less than and greater than a respective critical Blech length constant. An occurrence of a void within the feeder line or the test line indicates that the layer material is permeable or impermeable.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christine Hau-Riege, Stefan Hau-Riege, Amit P. Marathe
  • Publication number: 20040056073
    Abstract: A method is provided for forming a wafer stack. This may include providing a first wafer having a first plurality of metalized trenches on a surface of the first wafer. A second wafer may be provided having a second plurality of metalized trenches on a surface of the second wafer facing the first wafer. The first plurality of metalized trenches may be solder bonded to the second plurality of metalized trenches.
    Type: Application
    Filed: September 25, 2003
    Publication date: March 25, 2004
    Inventors: Stefan Hau-Riege, Christine Hau-Riege
  • Patent number: 6667225
    Abstract: A method is provided for forming a wafer stack. This may include providing a first wafer having a first plurality of metalized trenches on a surface of the first wafer. A second wafer may be provided having a second plurality of metalized trenches on a surface of the second wafer facing the first wafer. The first plurality of metalized trenches may be solder bonded to the second plurality of metalized trenches.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Stefan Hau-Riege, Christine Hau-Riege