Abstract: A verification system for an integrated device includes a plurality of detailed subsystem virtual prototypes, a plurality of fast subsystem virtual prototypes, and a test controller. The plurality of detailed system virtual prototypes include simulation information for core functionality of subsystems of the device. The plurality of fast system level prototypes include simulation information to facilitate overall functionality of the combined subsystems of the device.

Abstract: A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex intermediate frequency signal can be derived. Connected downstream of the first mixer stage is a limiting amplifier at whose output the intermediate frequency signal is present in a discrete-value and continuous-time fashion. A sampling device, for sampling the intermediate frequency signal, and a digital demodulator unit are connected to the output of this limiter. The demodulated input signal can be derived at the output of this digital demodulator unit. The present radio receiver requires a low chip area in conjunction with low power consumption, but offers a high sensitivity and accuracy based on the digitally implemented demodulation.

Abstract: In a receiver circuit for demodulating a high-frequency signal, a limiting amplifier stage with a downstream sigma-delta converter is connected in series with a mixer stage that transforms a high-frequency signal that is supplied at its input into an intermediate-frequency signal. The intermediate-frequency signal at the output of the limiting amplifier stage is value-discrete and time-continuous. The described receiver architecture has a high sensitivity, is substantially independent of production tolerances, and occupies a small area; therefore, it is particularly suitable for mobile radio applications.

Abstract: A demodulator has a resistor and a capacitor that may be subject to tolerances. For tolerance correction, the FM demodulator is preferably supplied with a reference frequency, which corresponds to the nominal mid-frequency of the demodulator, which is a function of the resistor and the capacitor. Any discrepancy between the actual mid-frequency of the demodulator and its nominal mid-frequency leads to the production of a voltage that differs from a nominal voltage at the output. A detector detects this error and adjusts the values of the resistor or capacitor until the error between the nominal voltage and the voltage is zero or is a minimum. The described principle can be used, for example, in integrated mobile radio receivers.

Abstract: A transmit frequency is generated for a transceiver by a controllable oscillator which generates an oscillator frequency, a divider by a factor N, and a mixer stage with a subsequent band filter. Signals with the oscillator frequency and the oscillator frequency divided by the factor N are to the mixer stage to generate an output signal at the transmit frequency.

Abstract: A digital telecommunication facility has a base station and one or more cordless mobile units. The telecommunication facility exchanges data between the mobile units and the base station in units of two or more TDMA frames.

Abstract: In the digital multi-subscriber radio telecommunication system which operates using frequency hopping technology and is intended for use in the 2.4 GHz ISM (Industrial Scientific and Medical) frequency band, in which a 20 dB channel bandwidth of a maximum of 1 MHz is prescribed, the known, DECT radio system operating using TDMA/FDMA technology is matched, in RF terms, to the ISM band and is modified such that the data transfer rate is reduced, preferably halved, by comparison with the data transfer rate of 1152 kbit/s, which is prescribed as standard for DECT. The system according to the invention can be used in cordless telephones.

Abstract: A circuit is provided for time division duplexing with a frequency hopping technique and has a total of just two frequency synthesizers for the transmission and reception paths and only one up-converter in the transmission path. The UHF synthesizer frequency is additionally subjected to frequency division prior to insertion as a heterodyne frequency of the assigned converter in the transmission and reception paths, which, owing to the shorter transient recovery times, makes it possible to utilize the UHF frequency synthesizers at different frequencies for the transmission and reception slots, respectively. A particular application is in cordless telephones.

Abstract: A demodulator has a resistor and a capacitor that may be subject to tolerances. For tolerance correction, the FM demodulator is preferably supplied with a reference frequency, which corresponds to the nominal mid-frequency of the demodulator, which is a function of the resistor and the capacitor. Any discrepancy between the actual mid-frequency of the demodulator and its nominal mid-frequency leads to the production of a voltage that differs from a nominal voltage at the output. A detector detects this error and adjusts the values of the resistor or capacitor until the error between the nominal voltage and the voltage is zero or is a minimum. The described principle can be used, for example, in integrated mobile radio receivers.

Abstract: A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex intermediate frequency signal can be derived. Connected downstream of the first mixer stage is a limiting amplifier at whose output the intermediate frequency signal is present in a discrete-value and continuous-time fashion. A sampling device, for sampling the intermediate frequency signal, and a digital demodulator unit are connected to the output of this limiter. The demodulated input signal can be derived at the output of this digital demodulator unit. The present radio receiver requires a low chip area in conjunction with low power consumption, but offers a high sensitivity and accuracy based on the digitally implemented demodulation.

Abstract: In a receiver circuit for demodulating a high-frequency signal, a limiting amplifier stage with a downstream sigma-delta converter is connected in series with a mixer stage that transforms a high-frequency signal that is supplied at its input into an intermediate-frequency signal. The intermediate-frequency signal at the output of the limiting amplifier stage is value-discrete and time-continuous. The described receiver architecture has a high sensitivity, is substantially independent of production tolerances, and occupies a small area; therefore, it is particularly suitable for mobile radio applications.

Abstract: For the purpose of error masking, binary representation of parameter values are precoded at the transmitting end by a linear block code before transmission over a faulty channel, and the redundant information added in this way is not used at the receiving end for error detection within the binary parameter representations, but is utilized in the course of a parameter estimation to improve the quality of the estimated parameter values.

Abstract: A method of encoding a signal, particularly a message signal for speech and/or image transmission, in which signal-matched encoding of the signal with M bits is performed using Q quantization levels, with Q<2M, and in which at least part of the remaining bit rate or the entire redundancy of M−Id(Q) bits is used to protect the signal against errors. The error protection uses a nonlinear code, for example. Furthermore, additional, signal-matched code redundancy can be added to an arbitrary source-coded signal. To decode the redundant signals in both cases, parameter estimation is performed at the receiving end using at least part of the redundancy.

Abstract: An FM receiver, which contains quadrature downward mixing to a low IF, analog IF polyphase filters in quadrature signal paths and an analog quadrature signal demodulator, has AC coupling in its two quadrature signal paths. At its output, the demodulator produces a voltage that is proportional to the input frequency and is supplied to the input of a decision circuit that determines the digital signal state. The circuit according to the invention can be used in DECT receivers.

Abstract: A circuit configuration of a frequency divider includes a prescaler with at least two different division ratios and at least two further different division ratios. A main counter connected to an output of the prescaler has an adjustable division ratio. A first lower-level swallow counter has an adjustable division ratio and can change the division ratio of the prescaler. At least one second lower-level swallow counter has an adjustable division ratio, is provided at the output of the main counter and can change the division ratio of the prescaler between the two further division ratios.

Abstract: A digital telecommunication facility has a base station and one or more cordless mobile units that communicate with the base station through a TDMA process. The mobile units and the base station change the transmitting/receiving frequency within which they communicate only once per TDMA frame and the retain the new transmitting/receiving frequency for a time corresponding to an entire TDMA frame.

Abstract: A digital telecommunications system has a base station and one or more wireless mobile parts. The mobile parts and the base station communicate according to the TDMA method. The frames of the TDMA method used in the telecommunications system have time slots of different lengths alternately succeeding one another within a TDMA frame.

Abstract: For the purpose of error masking, binary representations of parameter values are precoded at the transmitting end by a linear block code before transmission over a faulty channel, and the redundant information added in this way is not used at the receiving end for error detection within the binary parameter representations, but is utilized in the course of a parameter estimation to improve the quality of the estimated parameter values.

Abstract: In the novel speech coding method and device, speech signals are coded by a combination of speech parameters and excitation signals. The speech parameters or excitation signals are described with vectors. The vectors are formed by superposing at least two tracks, wherein at least one track has at least two vector elements different from zero. The algebraic signs of the vector elements that differ from zero are coded independently of one another and independently of the positions of the vector elements that differ from zero.

Abstract: The ON and OFF states of a second device are controlled by a first device through a three-conductor bus. The bus carries data, clock, and enable signals and the second device is in the OFF state when all the signals of the three-conductor bus have an L level. The second device is in the ON state when at least one of the signals has an H level (higher potential than the L level). The enable signal is set to the H level during the data transmission. Otherwise, it carries an L level, while the data or clock signal has an H level. The system obviates an additional housing pin. The operating state information is transmitted relatively rapidly.