Patents by Inventor Stefan Herzer

Stefan Herzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220381196
    Abstract: The invention relates to a method for the operational analysis of an engine and/or for calibrating a controller of the engine, in particular an internal combustion engine, wherein run-up occurs of test points defined by values of a plurality of predetermined operating parameters and selected from a multidimensional test space using a statistical experiment design, whereby at least one operating parameter is in each case changed from one test point to the next test point in a plurality of steps in the run-up of the test points, wherein operational measurements are performed at measurement points resulting from a respective increment and at the actual test points, whereby measurement data from the operational measurements for the analysis and calibration of the controller are output and continuously stored, as well as a corresponding system.
    Type: Application
    Filed: November 12, 2020
    Publication date: December 1, 2022
    Inventors: Marie-Sophie GANDE, Stefan SCHEIDEL, Philip WILLIAMS, Andreas WAGNER, Takuya SATO, Yoann COLLET, Helmut Peter GRASSBERGER, Mats IVARSON, Ganesh BALACHANDRAN, Markus HERZER
  • Publication number: 20220244638
    Abstract: A permanent resist, such as TMMF, is used when patterning conductive material on a substrate, enabling lines that have a higher line-to-space ratio (L/S) or a higher aspect ratio (T/L) or both. Pattern density can thus be increased, allowing for improved performance (e.g., greater efficiency, in the case of transformer coil patterning) and greater heat dissipation. As examples, the permanent-resist-based patterning fabrication methods can be used to create transformer coils within an integrated circuit (IC) module, or a routable lead frame for one or more IC dies.
    Type: Application
    Filed: October 28, 2021
    Publication date: August 4, 2022
    Inventors: Hidetoshi Inoue, Kenji Kawano, Yuki Sato, Takafumi Ando, Michael Lueders, Stefan Herzer, Jeffrey Morroni
  • Publication number: 20220158537
    Abstract: In some examples, a circuit includes a resistor network, a filter, a current generator, and a capacitor. The resistor network has a resistor network output and is adapted to be coupled between a switch terminal of a power converter (104) and a ground terminal. The filter has a filter input and a filter output, the filter input coupled to the resistor network output. The current generator has a current generator output and first and second current generator inputs, the first current generator input configured to receive an input voltage and the second current generator input coupled to the filter output. The capacitor is coupled between the current generator output and the ground terminal.
    Type: Application
    Filed: March 26, 2021
    Publication date: May 19, 2022
    Inventors: Zhangyi Xie, Neil Gibson, Stefan Herzer
  • Publication number: 20220158554
    Abstract: In some examples, a circuit comprises a first field effect transistor (FET) having a first gate adapted to couple to a reference voltage source, a first source coupled to a first current source, and a first drain coupled to a second current source. The circuit comprises a second FET having a second gate coupled to the first drain, a second drain coupled to the first current source, and a second source coupled to a first resistor. The circuit comprises a third FET having a third gate adapted to couple to a feedback loop of a voltage converter, a third source coupled to a third current source, and a third drain coupled to a fourth current source. The circuit comprises a fourth FET having a fourth gate coupled to the third drain, a fourth drain coupled to the third current source, and a fourth source coupled to a second resistor.
    Type: Application
    Filed: November 17, 2020
    Publication date: May 19, 2022
    Inventors: Neil GIBSON, Stefan HERZER
  • Publication number: 20220059439
    Abstract: A method includes performing a non-screen printing process that deposits solder on a lead frame or on conductive features of a semiconductor die or wafer, or on or in a conductive via of a laminate structure. The method further comprises engaging the semiconductor die to the lead frame, performing a thermal process that reflows the solder, performing a molding process that forms a package structure which encloses the semiconductor die and a portion of the lead frame, and separating a packaged electronic device from a remaining portion of the lead frame.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Robert Allan Neidorff, Benjamin Cook, Stefan Herzer
  • Patent number: 11195958
    Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: December 7, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Alexei Sadovnikov, Abbas Ali, Yanbiao Pan, Stefan Herzer
  • Publication number: 20210344272
    Abstract: A voltage regulation circuit includes a switching output terminal, a high-side output transistor, a low-side output transistor, a high-side replica transistor, a low-side replica transistor, and a comparator circuit. The high-side output transistor is configured to drive the switching output terminal. The low-side output transistor is configured to drive the switching output terminal. The high-side replica transistor is coupled to the high-side output transistor. The low-side replica transistor is coupled to the high-side replica transistor and the low-side output transistor. The comparator circuit is coupled to the high-side replica transistor and the low-side replica transistor, and is configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor to a ramp signal.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 4, 2021
    Inventors: Neil GIBSON, Stefan HERZER
  • Patent number: 11139365
    Abstract: An integrated circuit comprising: a source comprising an output port; a set of serially-connected resistors electrically coupled to the output port of the source; a comparator comprising a first input port, a second input port, and an output port; a set of switches, each switch in the set of switches comprising a first terminal electrically coupled to the first input port of the comparator, and a second terminal electrically coupled to the set of serially-connected resistors; a current source comprising an output port electrically coupled to the second input port of the comparator; and a pin electrically coupled to the output port of the current source.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Uwe Schlenker, Stefan Herzer, Konrad Wagensohner
  • Patent number: 11095220
    Abstract: A voltage regulation circuit includes a switching output terminal, a high-side output transistor, a low-side output transistor, a high-side replica transistor, a low-side replica transistor, and a comparator circuit. The high-side output transistor is configured to drive the switching output terminal. The low-side output transistor is configured to drive the switching output terminal. The high-side replica transistor is coupled to the high-side output transistor. The low-side replica transistor is coupled to the high-side replica transistor and the low-side output transistor. The comparator circuit is coupled to the high-side replica transistor and the low-side replica transistor, and is configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor to a ramp signal.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 17, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Neil Gibson, Stefan Herzer
  • Publication number: 20210159787
    Abstract: A voltage regulation circuit includes a switching output terminal, a high-side output transistor, a low-side output transistor, a high-side replica transistor, a low-side replica transistor, and a comparator circuit. The high-side output transistor is configured to drive the switching output terminal. The low-side output transistor is configured to drive the switching output terminal. The high-side replica transistor is coupled to the high-side output transistor. The low-side replica transistor is coupled to the high-side replica transistor and the low-side output transistor. The comparator circuit is coupled to the high-side replica transistor and the low-side replica transistor, and is configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor to a ramp signal.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Neil GIBSON, Stefan HERZER
  • Patent number: 10992229
    Abstract: An electrical system includes: 1) a buck converter; 2) a battery coupled to an input of the buck converter; and 3) a load coupled to an output of the buck converter. The buck converter includes a high-side switch, a low-side switch, and regulation loop circuitry coupled to the high-side switch and the low-side switch. The regulation loop circuitry includes a comparator with preamplifier gain adjustment circuitry configured to adjust a preamplifier gain of the comparator based on an overdrive voltage.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 27, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Gerhard Thiele, Manuel Wiersch, Antonio Priego, Johann Erich Bayer, Stefan Herzer
  • Publication number: 20210066229
    Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.
    Type: Application
    Filed: November 10, 2020
    Publication date: March 4, 2021
    Inventors: PATRICK FRANCIS THOMPSON, CHRISTOPHER DANIEL MANACK, STEFAN HERZER, RAKSHIT AGRAWAL
  • Publication number: 20210005760
    Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Inventors: Binghua Hu, Alexei Sadovnikov, Abbas Ali, Yanbiao Pan, Stefan Herzer
  • Patent number: 10833036
    Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Patrick Francis Thompson, Christopher Daniel Manack, Stefan Herzer, Rakshit Agrawal
  • Patent number: 10811543
    Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Alexei Sadovnikov, Abbas Ali, Yanbiao Pan, Stefan Herzer
  • Publication number: 20200211992
    Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 2, 2020
    Inventors: PATRICK FRANCIS THOMPSON, CHRISTOPHER DANIEL MANACK, STEFAN HERZER, RAKSHIT AGRAWAL
  • Publication number: 20200212229
    Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: Binghua Hu, Alexei Sadovnikov, Abbas Ali, Yanbiao Pan, Stefan Herzer
  • Publication number: 20200127570
    Abstract: An electrical system includes: 1) a buck converter; 2) a battery coupled to an input of the buck converter; and 3) a load coupled to an output of the buck converter. The buck converter includes a high-side switch, a low-side switch, and regulation loop circuitry coupled to the high-side switch and the low-side switch. The regulation loop circuitry includes a comparator with preamplifier gain adjustment circuitry configured to adjust a preamplifier gain of the comparator based on an overdrive voltage.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 23, 2020
    Inventors: Gerhard THIELE, Manuel WIERSCH, Antonio PRIEGO, Johann Erich BAYER, Stefan HERZER
  • Patent number: 10615693
    Abstract: A system comprises a DC-to-DC voltage converter, the DC-to-DC voltage converter comprising: a high-side FET comprising a gate, a source, and a drain; a node coupled to the source of the high-side FET; a low-side FET comprising a gate, a source, and a drain coupled to the node; and a controller coupled to the gate of the high-side FET to switch on and off the high-side FET, and coupled to the gate of the low-side FET to switch on and off the low-side FET, the controller configured to switch on the low-side FET for a time interval before switching on the high-side FET and to switch off the low-side FET before switching on the high-side FET.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 7, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Syed Wasif Mehdi, Stefan Herzer, Antonio Priego
  • Publication number: 20200007035
    Abstract: A system comprises a DC-to-DC voltage converter, the DC-to-DC voltage converter comprising: a high-side FET comprising a gate, a source, and a drain; a node coupled to the source of the high-side FET; a low-side FET comprising a gate, a source, and a drain coupled to the node; and a controller coupled to the gate of the high-side FET to switch on and off the high-side FET, and coupled to the gate of the low-side FET to switch on and off the low-side FET, the controller configured to switch on the low-side FET for a time interval before switching on the high-side FET and to switch off the low-side FET before switching on the high-side FET.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Syed Wasif MEHDI, Stefan Herzer, Antonio PRIEGO