Abstract: A circuit includes a half-bridge circuit configured to provide a switching voltage responsive to respective high-side and low-side drive signals. High-side slew control circuitry is configured to provide a high-side slew-compensated control signal responsive to a high-side enable signal and a slew current signal representative of a slew rate at a switching output. A high-side driver is configured to provide the high-side drive signal responsive to the high-side slew-compensated control signal. Low-side slew control circuitry is configured to provide a low-side slew-compensated drive signal responsive to a low-side enable signal and the slew current signal. A low-side driver is configured to provide the low-side drive signal responsive to the low-side slew-compensated control signal. A capacitor is coupled between the high-side and low-side slew control circuitry and is configured to convert the slew rate to the slew current signal.

Abstract: In one example, an apparatus comprises: a first transistor having a first control terminal and first and second current terminals; a capacitor coupled between a switching terminal and the first current terminal; a second transistor having a second control terminal and coupled between the switching terminal and a ground terminal; and a sensing and control circuit having a power terminal, a third current terminal, an enable input and a transistor control output, the third current terminal coupled to the second current terminal, the enable input coupled to the second control terminal, and the transistor control output coupled to the first control terminal.

Abstract: An integrated circuit includes an error amplifier having a reference input, a feedback input, and an error output. A comparator has first and second comparator inputs and a comparator output. The first comparator input is coupled to the error output. A control circuit has a control input and a control output. The control input is coupled to the comparator output. The compensation circuit has a compensation control input and a compensation output. The compensation control input is coupled to the control output. The compensation output is coupled to at least one of the reference input, the feedback input, or the error output.

Abstract: In described examples, an integrated circuit includes first and second current sources, first and second switches, a dV/dt phase detector, a control circuit, and source, gate, and drain terminals for coupling to, respectively, a source, gate, and drain of a power FET. The first switch is coupled between the first current source and the gate terminal. The second switch is coupled between the second current source and the gate terminal. The dV/dt phase detector detects a dV/dt phase of the power FET and outputs to the control circuit. The control circuit controls the first and second switches to perform a turn-on sequence of the power FET, including: closing the first switch while keeping the second switch open; and after receiving a signal from the dV/dt phase detector indicating the dV/dt phase has started, opening the first switch, and closing the second switch.

Abstract: A circuit includes a first transistor coupled between a first power terminal and a switching terminal and having a first control terminal, a second transistor coupled between the switching terminal and a ground terminal and having a second control terminal, and a third transistor coupled between the switching terminal and the ground terminal and having a third control terminal. The circuit also includes a driver circuit having a driver input and first, second, and third driver outputs, the first driver output coupled to the first control terminal, the second driver output coupled to the second control terminal, and the third driver output coupled to the third control terminal. The circuit further includes a discharge control circuit having a second power terminal, a control input, and a control output, the control input coupled to the switching terminal, and the control output coupled to the third control terminal.

Abstract: A circuit includes a first transistor coupled between a discharge terminal and a ground terminal. The first transistor has a first control terminal. A resistor is coupled between a power terminal and the first control terminal. A second transistor has a second control terminal coupled to the discharge terminal. A rectifying device is coupled between the resistor and the second transistor.

Abstract: A circuit includes a half-bridge circuit is configured to provide a switching voltage responsive to respective high-side and low-side drive signals. High-side slew control circuitry is configured to provide a high-side slew-compensated control signal responsive to a high-side enable signal and a slew current signal representative of a slew rate at a switching output. A high-side driver is configured to provide the high-side drive signal responsive to the high-side slew-compensated control signal. Low-side slew control circuitry is configured to provide a low-side slew-compensated drive signal responsive to a low-side enable signal and the slew current signal. A low-side driver is configured to provide the low-side drive signal responsive to the low-side slew-compensated control signal. A capacitor is coupled between the high-side and low-side slew control circuitry and is configured to convert the slew rate to the slew current signal.

Abstract: A circuit includes a switching converter, an oscillator, and a spread spectrum modulator (SSM). The oscillator has a modulation input and a clock output. The clock output is coupled to the switching converter. The oscillator is configured to generate a clock signal at the clock output having a frequency based on a modulation signal at the modulation input. The SSM has a modulation output coupled to the modulation input of the oscillator. The SSM is configured to generate the modulation signal at the modulation output while adjusting a rate of change of the modulation signal based on a magnitude of the modulation signal at a boundary of a modulation time period.

Abstract: An apparatus includes a first transistor having a control terminal. A second transistor couples in series with the first transistor. A driver has a first, second, and third driver terminals, and a driver output. The driver output couples to the control terminal. A capacitor has a first and second capacitor terminals. The first capacitor terminal couples to the first driver terminal, and the second capacitor terminal couples to the second driver terminal and to the first and second transistors. A third transistor has a first and second transistor terminals. The first transistor terminal couples to the first capacitor terminal, and the second transistor terminal couples to the third driver terminal. A fourth transistor has third and fourth transistor terminals. The third transistor terminal couples to the second transistor terminal.

Abstract: A self-biasing circuit for power converters is disclosed. In an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. The first transistor has a first control terminal, and the second transistor has a second control terminal. In an example, the first and second transistors are configured to split a current at the inductor terminal. The apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.

Abstract: A ground reference circuit to generate a ground reference for a voltage reference circuit includes a resistor coupled in series with a transistor via a current mirror. The resistor is coupled between a ground reference terminal of the voltage reference circuit and a ground terminal of a power converter. The transistor control terminal is configured to receive a pulse width modulation (PWM) control signal having a duty cycle similar to a switching element duty cycle of the power converter. The current mirror circuit is coupled between a current terminal of the transistor and the ground reference terminal. A controller configured to control the switching element duty cycle may include the ground reference circuit, along with the voltage reference circuit, and a PWM circuit configured to determine the switching element duty cycle based on a comparison between a reference voltage provided by the voltage reference circuit and the converter output voltage.

Abstract: A circuit includes a transistor and a ringing control circuit. The transistor is coupled between an input voltage terminal and a switching terminal. The transistor includes a control terminal. The ringing control circuit has a control input and a control output. The control input is coupled to the switching terminal, and the control output is coupled to the control terminal.

Abstract: Techniques for valley detection in flyback power converters. In an example, circuitry implementing the techniques is configured to generate a first indication of an over-voltage protection (OVP) condition of a flyback power converter, using a switching terminal signal of the flyback power converter. The circuitry is further configured to generate a second indication of an input voltage surge condition of the flyback power converter, using the switching terminal signal of the flyback power converter. The circuitry further is further configured to suppress the first indication, responsive to the second indication being generated.

Abstract: A packaged integrated circuit (IC) including a semiconductor die having a metallization layer, the metallization layer including first metal interconnects in a first insulation material. The IC includes a first substrate on the metallization layer, the first substrate including second metal interconnects in a second insulation material different from the first insulation material, at least one of the second metal interconnects being electrically coupled to at least one of the first metal interconnects. The IC further includes a second substrate on the first substrate, the second substrate including an isolation circuit and third metal interconnects in a third insulation material different from the first insulation material, the isolation circuit being electrically coupled to the at least one of the first metal interconnects via the at least one of the second metal interconnects and at least one of the third metal interconnects.

Abstract: A self-biasing circuit for power converters is disclosed. In an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. The first transistor has a first control terminal, and the second transistor has a second control terminal. In an example, the first and second transistors are configured to split a current at the inductor terminal. The apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.

Abstract: An apparatus comprising a first switch coupled between a first power terminal and a first inverter terminal, the first switch having a first switch control input. A second switch is coupled between the first inverter terminal and a second power terminal, the second switch having a second switch control input. A third switch is coupled between the second power terminal and a second inverter terminal, the third switch having a third switch control input. A fourth switch is coupled between the second inverter terminal and a reference terminal, the fourth switch having a fourth switch control input. An inverter circuit is coupled between first and second inverter terminals, the inverter circuit having outputs coupled to primary side terminals.

Abstract: An apparatus comprising a current source having a current control input and a current source output, the current source output coupled to a first transistor control terminal. The apparatus further comprises a transistor coupled between the first transistor control terminal and a current drain (or sink) terminal, the transistor having a second transistor control terminal. The apparatus further comprises an amplifier having a first input, a second input, and an amplifier output, the first input coupled to the first transistor control terminal, the second input coupled to a reference terminal, and the amplifier output coupled to the current control input and the second transistor control terminal.

Abstract: In one example, an apparatus comprises: a first transistor having a first control terminal and first and second current terminals; a capacitor coupled between a switching terminal and the first current terminal; a second transistor having a second control terminal and coupled between the switching terminal and a ground terminal; and a sensing and control circuit having a power terminal, a third current terminal, an enable input and a transistor control output, the third current terminal coupled to the second current terminal, the enable input coupled to the second control terminal, and the transistor control output coupled to the first control terminal.

Abstract: A ground reference circuit to generate a ground reference for a voltage reference circuit includes a resistor coupled in series with a transistor via a current mirror. The resistor is coupled between a ground reference terminal of the voltage reference circuit and a ground terminal of a power converter. The transistor control terminal is configured to receive a pulse width modulation (PWM) control signal having a duty cycle similar to a switching element duty cycle of the power converter. The current mirror circuit is coupled between a current terminal of the transistor and the ground reference terminal. A controller configured to control the switching element duty cycle may include the ground reference circuit, along with the voltage reference circuit, and a PWM circuit configured to determine the switching element duty cycle based on a comparison between a reference voltage provided by the voltage reference circuit and the converter output voltage.

Abstract: An example apparatus includes: a first transistor implemented using Gallium Nitride (GaN), the first transistor having: a drain configured to receive an input voltage from a power supply; a gate configured to receive a voltage from control circuitry; and a source; a second transistor implemented using GaN, the second transistor having: a drain coupled to the source of the first transistor; a gate coupled to a current source; and a source configured to provide an output voltage based on a voltage at the source of the first transistor; and a third transistor implemented using GaN, the third transistor having: a drain coupled to the source of the first transistor and the drain of the second transistor; a gate; and a source configured to be coupled to ground.