Abstract: The present disclosure generally relates to a semiconductor device having a slanted field plate. In an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on a surface of the semiconductor substrate. The drain contact and a source contact are on the semiconductor substrate. The field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. The field plate includes multiple field plate portions. Each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.

Abstract: A ground reference circuit to generate a ground reference for a voltage reference circuit includes a resistor coupled in series with a transistor via a current mirror. The resistor is coupled between a ground reference terminal of the voltage reference circuit and a ground terminal of a power converter. The transistor control terminal is configured to receive a pulse width modulation (PWM) control signal having a duty cycle similar to a switching element duty cycle of the power converter. The current mirror circuit is coupled between a current terminal of the transistor and the ground reference terminal. A controller configured to control the switching element duty cycle may include the ground reference circuit, along with the voltage reference circuit, and a PWM circuit configured to determine the switching element duty cycle based on a comparison between a reference voltage provided by the voltage reference circuit and the converter output voltage.

Abstract: A circuit includes a first transistor and a ringing control circuit. The first transistor is coupled between a power terminal and a switching terminal. The first transistor includes a first control terminal. The ringing control circuit is coupled between the power terminal and the first control terminal. The ringing control circuit includes a second transistor and a variable resistance circuit. The second transistor is coupled between the power terminal and the first control terminal. The second transistor has a second control terminal. The variable resistance circuit is coupled between the second control terminal and the switching terminal. The variable resistance circuit includes a control input coupled to the power terminal.

Abstract: An integrated circuit includes an error amplifier having a reference input, a feedback input, and an error output. A comparator has first and second comparator inputs and a comparator output. The first comparator input is coupled to the error output. A control circuit has a control input and a control output. The control input is coupled to the comparator output. The compensation circuit has a compensation control input and a compensation output. The compensation control input is coupled to the control output. The compensation output is coupled to at least one of the reference input, the feedback input, or the error output.

Abstract: A self-biasing circuit for power converters is disclosed. In an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. The first transistor has a first control terminal, and the second transistor has a second control terminal. In an example, the first and second transistors are configured to split a current at the inductor terminal. The apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.

Abstract: A circuit includes a first transistor coupled between a discharge terminal and a ground terminal. The first transistor has a first control terminal. A resistor is coupled between a power terminal and the first control terminal. A second transistor has a second control terminal coupled to the discharge terminal. A rectifying device is coupled between the resistor and the second transistor.

Abstract: A circuit includes a transistor and a ringing control circuit. The transistor is coupled between an input voltage terminal and a switching terminal. The transistor includes a control terminal. The ringing control circuit has a control input and a control output. The control input is coupled to the switching terminal, and the control output is coupled to the control terminal.

Abstract: In described examples, an integrated circuit includes first and second current sources, first and second switches, a dV/dt phase detector, a control circuit, and source, gate, and drain terminals for coupling to, respectively, a source, gate, and drain of a power FET. The first switch is coupled between the first current source and the gate terminal. The second switch is coupled between the second current source and the gate terminal. The dV/dt phase detector detects a dV/dt phase of the power FET and outputs to the control circuit. The control circuit controls the first and second switches to perform a turn-on sequence of the power FET, including: closing the first switch while keeping the second switch open; and after receiving a signal from the dV/dt phase detector indicating the dV/dt phase has started, opening the first switch, and closing the second switch.

Abstract: A gate driver circuit includes a charge pump circuit, a gate pull-up transistor, a resistor, and a capacitor. The charge pump circuit includes an output. The gate pull-up transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to the output of the charge pump circuit. The second current terminal is coupled to a gate drive output terminal. The resistor is coupled between the power input terminal and the control terminal. The capacitor is coupled between the control terminal and a ground terminal.

Abstract: A circuit includes a half-bridge circuit is configured to provide a switching voltage responsive to respective high-side and low-side drive signals. High-side slew control circuitry is configured to provide a high-side slew-compensated control signal responsive to a high-side enable signal and a slew current signal representative of a slew rate at a switching output. A high-side driver is configured to provide the high-side drive signal responsive to the high-side slew-compensated control signal. Low-side slew control circuitry is configured to provide a low-side slew-compensated drive signal responsive to a low-side enable signal and the slew current signal. A low-side driver is configured to provide the low-side drive signal responsive to the low-side slew-compensated control signal. A capacitor is coupled between the high-side and low-side slew control circuitry and is configured to convert the slew rate to the slew current signal.

Abstract: A voltage converter includes a switch network, a rectifier, and a transformer coupled between the switch network and the rectifier. The voltage converter includes an adaptive ON-time generation circuit having a control input and a control output, the control input. The adaptive ON-time generation circuit is configured to receive a WAKE signal to turn ON the switch network, generate a signal indicative of an OFF time of the switch network, and determine an ON time for the switch network based on the signal indicative of the OFF time.

Abstract: In some examples, a circuit includes a resistor network, a filter, a current generator, and a capacitor. The resistor network has a resistor network output and is adapted to be coupled between a switch terminal of a power converter (104) and a ground terminal. The filter has a filter input and a filter output, the filter input coupled to the resistor network output. The current generator has a current generator output and first and second current generator inputs, the first current generator input configured to receive an input voltage and the second current generator input coupled to the filter output. The capacitor is coupled between the current generator output and the ground terminal.

Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.

Abstract: A device includes a die with a metallization stack. The device includes a substrate with a first region, a second region and a third region that underly the metallization stack and a first isolation trench filled with a polymer dielectric that extends between the first region and the second region of the substrate. The device also includes a second isolation trench filled with the polymer dielectric that extends between the second region and the third region. The polymer dielectric overlays a periphery of the substrate.

Abstract: A voltage regulation circuit includes a switching output terminal, a high-side output transistor, a low-side output transistor, a high-side replica transistor, a low-side replica transistor, and a comparator circuit. The high-side output transistor is configured to drive the switching output terminal. The low-side output transistor is configured to drive the switching output terminal. The high-side replica transistor is coupled to the high-side output transistor. The low-side replica transistor is coupled to the high-side replica transistor and the low-side output transistor. The comparator circuit is coupled to the high-side replica transistor and the low-side replica transistor, and is configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor to a ramp signal.

Abstract: In some examples, a circuit comprises a first field effect transistor (FET) having a first gate adapted to couple to a reference voltage source, a first source coupled to a first current source, and a first drain coupled to a second current source. The circuit comprises a second FET having a second gate coupled to the first drain, a second drain coupled to the first current source, and a second source coupled to a first resistor. The circuit comprises a third FET having a third gate adapted to couple to a feedback loop of a voltage converter, a third source coupled to a third current source, and a third drain coupled to a fourth current source. The circuit comprises a fourth FET having a fourth gate coupled to the third drain, a fourth drain coupled to the third current source, and a fourth source coupled to a second resistor.

Abstract: A permanent resist, such as TMMF, is used when patterning conductive material on a substrate, enabling lines that have a higher line-to-space ratio (L/S) or a higher aspect ratio (T/L) or both. Pattern density can thus be increased, allowing for improved performance (e.g., greater efficiency, in the case of transformer coil patterning) and greater heat dissipation. As examples, the permanent-resist-based patterning fabrication methods can be used to create transformer coils within an integrated circuit (IC) module, or a routable lead frame for one or more IC dies.

Abstract: In some examples, a circuit includes a resistor network, a filter, a current generator, and a capacitor. The resistor network has a resistor network output and is adapted to be coupled between a switch terminal of a power converter (104) and a ground terminal. The filter has a filter input and a filter output, the filter input coupled to the resistor network output. The current generator has a current generator output and first and second current generator inputs, the first current generator input configured to receive an input voltage and the second current generator input coupled to the filter output. The capacitor is coupled between the current generator output and the ground terminal.

Abstract: In some examples, a circuit comprises a first field effect transistor (FET) having a first gate adapted to couple to a reference voltage source, a first source coupled to a first current source, and a first drain coupled to a second current source. The circuit comprises a second FET having a second gate coupled to the first drain, a second drain coupled to the first current source, and a second source coupled to a first resistor. The circuit comprises a third FET having a third gate adapted to couple to a feedback loop of a voltage converter, a third source coupled to a third current source, and a third drain coupled to a fourth current source. The circuit comprises a fourth FET having a fourth gate coupled to the third drain, a fourth drain coupled to the third current source, and a fourth source coupled to a second resistor.

Abstract: A method includes performing a non-screen printing process that deposits solder on a lead frame or on conductive features of a semiconductor die or wafer, or on or in a conductive via of a laminate structure. The method further comprises engaging the semiconductor die to the lead frame, performing a thermal process that reflows the solder, performing a molding process that forms a package structure which encloses the semiconductor die and a portion of the lead frame, and separating a packaged electronic device from a remaining portion of the lead frame.