Abstract: A method and a system for providing information for recovering a clock frequency via a data network comprise generating a value representative of a frequency difference between a clock frequency and a reference frequency by using a digital phase-locked loop at an ingress interface of a data network, transmitting the generated value over the data network, and recovering the clock frequency at an egress interface of the data network by using the reference frequency and the transmitted value. Other systems and methods are also disclosed.

Abstract: At an ingress interface of a data network first information data are generated, at an egress interface of the data network second information data are generated, correction data are generated on the basis of the second information data, and at the egress interface a clock frequency is recovered on the basis of the first information data and the correction data.

Abstract: A method and device for controlling the phase of successively transmitted frames, in which data symbols are transmitted at a constant symbol frequency, in which a phase difference between the clock of the frame transmission and a data clock is determined and, dependent on the phase difference, an adjusting signal is produced for controlling the injection of stuffing data symbols into the frames for changing the frame length and the phase of the frame transmission, whereby the phase of the frame transmission is controlled so that the frames are transmitted on average synchronously with the data clock, wherein the adjusting signal is produced dependent on the phase difference determine from N frame in each successively transmitted, whereby N is at least 2.

Abstract: At an ingress interface of a data network first information data are generated, at an egress interface of the data network second information data are generated, correction data are generated on the basis of the second information data, and at the egress interface a clock frequency is recovered on the basis of the first information data and the correction data.

Abstract: A method and a system for providing information for recovering a clock frequency via a data network comprise generating a value representative of a frequency difference between a clock frequency and a reference frequency by using a digital phase-locked loop at an ingress interface of a data network, transmitting the generated value over the data network, and recovering the clock frequency at an egress interface of the data network by using the reference frequency and the transmitted value. Other systems and methods are also disclosed.

Abstract: A method and a device are presented for generating a system clock (OC) of a transmitting and/or receiving device with the aid of a system oscillator (1, 2). At least one control signal (PS, FS, JS, IS) is thereby evaluated by an evaluation unit (12) and the system oscillator (1, 11) is actuated as a function of this control signal (PS, FS, JS, IS) in order to change its frequency. This makes it possible for problems which arise due to an excessive frequency tolerance of an oscillating quartz element (1) to be eliminated or avoided by preventive means.

Abstract: With plesiochronous data communication, as in particular S(H)DSL transmission, data symbols (2) are transmitted at a constant symbol frequency in frames (1) with a time duration variable within limits. The length of the frames (1) is varied by inserting or omitting stuffing data symbols in relation to a nominal length, so that it is averaged over several frames (1) synchronously with a data clock. If the data clock frequency is synchronous with the symbol frequency, alternating stuffing data symbols are injected or omitted in the frames (1), so that the phase of the frames (1) varies constantly during the transmission. This variation however occurs at a high frequency and can be easily suppressed on the receiving side when recovering the data clock by means of a PLL.