Abstract: For the verification of digital circuits, which can have multiplier structures in particular, an equivalence test between the digital circuit and a reference description of this digital circuit is proposed, in such a way that firstly for the multiplier structures implemented in the digital circuit the realized implementation alternative of several pre-defined different implementation alternatives is determined in each case and inserted into the reference description in place of the respective multiplication function, in order subsequently to execute the equivalence test with the reference description changed thereby. In this way, the structural equivalence between the reference description and the digital circuit to be verified can be substantially increased, which speeds up the verification process overall.

Abstract: A system and method for locating circuit deviations or circuit faults in a circuit in respect of a reference circuit. The circuit and the reference circuit are respectively describable by signal-flow graphs, the signal-flow graphs being composed of a multiplicity of interconnected function blocks. The function blocks of the circuit are first assigned to corresponding function blocks of the reference circuit. There are then ascertained those function blocks of the circuit and of the reference circuit for which assignment has not been possible, and which have disposed upstream in the signal flow at least one function block for which assignment has been possible. The result is a boundary between an assigned and a non-assigned region of the circuit and the reference circuit, respectively. A representation of the circuit and reference circuit is preferably produced in which the regions corresponding to the non-assigned function blocks are highlighted.

Abstract: The invention permits a comparison of two technical systems, which according to conventional opinion is not possible to carry out, based on a substantially simpler, technically achievable comparison, in which part systems of one or both systems are specifically replaced. The replacements are performed in a controlled manner by monitoring a replacement condition with constraints. The monitoring of the replacement condition and the generation and monitoring of the necessary constraints occur automatically. A comparison of both systems can thus be carried out based on the replacement of the part systems without introducing a loss of precision in the comparison.

Abstract: For the verification of digital circuits, which can have multiplier structures in particular, an equivalence test between the digital circuit and a reference description of this digital circuit is proposed, in such a way that firstly for the multiplier structures implemented in the digital circuit the realized implementation alternative of several pre-defined different implementation alternatives is determined in each case and inserted into the reference description in place of the respective multiplication function, in order subsequently to execute the equivalence test with the reference description changed thereby. In this way, the structural equivalence between the reference description and the digital circuit to be verified can be substantially increased, which speeds up the verification process overall.

Abstract: A system and method for locating circuit deviations or circuit faults in a circuit in respect of a reference circuit. The circuit and the reference circuit are respectively describable by signal-flow graphs, the signal-flow graphs being composed of a multiplicity of interconnected function blocks. The function blocks of the circuit are first assigned to corresponding function blocks of the reference circuit. There are then ascertained those function blocks of the circuit and of the reference circuit for which assignment has not been possible, and which have disposed upstream in the signal flow at least one function block for which assignment has been possible. The result is a boundary between an assigned and a non-assigned region of the circuit and the reference circuit, respectively. A representation of the circuit and reference circuit is preferably produced in which the regions corresponding to the non-assigned function blocks are highlighted.

Abstract: In order when designing a digital circuit to be able to determine the minimum or maximum switching activity for estimating the power consumption it is determined according to the invention on the basis of a model of the digital circuit whether there is a disproving operational case, in which the switching activity is less than an estimated value (k) for the minimum switching activity or greater than an estimated value (k) for the maximum switching activity. If the existence of an appropriate disproving operational case (P(k)) can be found, when determining the maximum switching activity the estimated value (k) is increased by one step size and when determining the minimum switching activity the estimated value (k) reduces. After a decrease or increase of the estimated value (k) the process is repeated and in this way the actual value for the maximum or minimum switching activity of the digital circuit is determined iteratively.

Abstract: In order when designing a digital circuit to be able to determine the minimum or maximum switching activity for estimating the power consumption it is determined according to the invention on the basis of a model of the digital circuit whether there is a disproving operational case, in which the switching activity is less than an estimated value (k) for the minimum switching activity or greater than an estimated value (k) for the maximum switching activity. If the existence of an appropriate disproving operational case (P(k)) can be found, when determining the maximum switching activity the estimated value (k) is increased by one step size and when determining the minimum switching activity the estimated value (k) reduces. After a decrease or increase of the estimated value (k) the process is repeated and in this way the actual value for the maximum or minimum switching activity of the digital circuit is determined iteratively.

Abstract: The invention permits a comparison of two technical systems, which according to conventional opinion is not possible to carry out, based on a substantially simpler, technically achievable comparison, in which part systems of one or both systems are specifically replaced. The replacements are performed in a controlled manner by monitoring a replacement condition with constraints. The monitoring of the replacement condition and the generation and monitoring of the necessary constraints occur automatically. A comparison of both systems can thus be carried out based on the replacement of the part systems without introducing a loss of precision in the comparison.