Abstract: A process for fabricating an electrically programmable read-only memory array having increased density includes forming recessed field oxide regions in a silicon substrate. Elongated parallel wordline stacks are then formed over the surface of the substrate. Source and drain regions are formed by ion implantation in the openings between these vertical stacks. These openings are then filled with a metal layer until the wafer is substantially planar. This metal layer is then patterned to form drain contact pads and V.sub.SS interconnect strips. The V.sub.SS interconnect strips contact adjacent source regions across field oxide regions that insulate adjacent memory cells.

Abstract: Improved processing which permits the simultaneous fabrication of block erasable flash EPROM cells and individually erasable EEPROM cells. A polysilicon finger extends from the floating gate of the EEPROM cell over a tunnel oxide region. Doped regions are formed under this finger by implanting dopants in alignment with the finger during the implantation of the source and drain regions for the cells and then driving the dopant under the finger. The arsenic dopant used to form the source and drain regions for the cells is used to form the doped regions along with the phosphorus dopant used for the source region of the flash EPROM cells.