Patents by Inventor Stefan KRAMP
Stefan KRAMP has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11926769Abstract: A reactive PSA film that includes: (a) a polymeric film former matrix; (b) one or more reactive components; and (c) a reagent selected from an initiator, a curing agent and an activator. The component (b) is present at a mass fraction of ?30%, as based on the sum of (a), (b) and (c). Further, ?50 wt % of the film former matrix is a crystallizable polymer which: (i) exhibits a crystallization enthalpy of <1 J/g in a DSC measurement on cooling at 10K/min from at least 30K above a peak temperature of the melting peak of the polymer or ?100° C., whichever is greater; and (ii) exhibits a crystallite fusion enthalpy of ?15 mJ/mg in its pure state in a first heating curve of a DSC measurement at 10K/min and after storage for ?one month from 15 to 25° C. and relative humidity from 30 to 70%.Type: GrantFiled: June 29, 2021Date of Patent: March 12, 2024Assignee: tesa SEInventors: Klaus Keite-Telgenbüscher, Frank Hannemann, Claudia Moehrke, Stefan Kramp
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Publication number: 20230420257Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.Type: ApplicationFiled: August 31, 2023Publication date: December 28, 2023Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Patent number: 11842938Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.Type: GrantFiled: November 30, 2021Date of Patent: December 12, 2023Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Patent number: 11798807Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.Type: GrantFiled: May 10, 2021Date of Patent: October 24, 2023Assignee: Infineon Technologies AGInventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Publication number: 20220093483Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.Type: ApplicationFiled: November 30, 2021Publication date: March 24, 2022Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Patent number: 11217500Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.Type: GrantFiled: April 9, 2019Date of Patent: January 4, 2022Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Publication number: 20210403767Abstract: A reactive PSA film that includes: (a) a polymeric film former matrix; (b) one or more reactive components; and (c) a reagent selected from an initiator, a curing agent and an activator. The component (b) is present at a mass fraction of 30%, as based on the sum of (a), (b) and (c). Further, ?50 wt % of the polymer film former matrix is a crystallizable polymer which: (i) exhibits a crystallization enthalpy of <1 J/g in a DSC measurement on cooling at 10 K/min from at least 30K above a peak temperature of the melting peak of the matrix and ?100° C.; and (ii) exhibits a crystallite fusion enthalpy of ?15 mJ/mg in its pure state in a first heating curve of a DSC measurement at 10 K/min and after storage for ? one month from 15 to 25° C. and relative humidity from 30 to 70%.Type: ApplicationFiled: June 29, 2021Publication date: December 30, 2021Applicant: tesa SEInventors: Klaus Keite-Telgenbüscher, Frank Hannemann, Claudia Moehrke, Stefan Kramp
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Publication number: 20210265168Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Patent number: 11043383Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.Type: GrantFiled: May 24, 2019Date of Patent: June 22, 2021Assignee: Infineon Technologies AGInventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Patent number: 10636754Abstract: A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, a semiconductor chip includes a chip front side, a first chip pad located on the chip front side, a second chip pad located on the chip front side and an electrically insulating material located between the first chip pad and the second chip pad, wherein the first chip pad includes a surface layer predominantly comprising copper and the second chip pad includes a surface layer predominantly comprising aluminum.Type: GrantFiled: January 30, 2019Date of Patent: April 28, 2020Assignee: Infineon Technologies AGInventors: Stefan Kramp, Marco Koitz
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Publication number: 20190362973Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.Type: ApplicationFiled: May 24, 2019Publication date: November 28, 2019Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Publication number: 20190311966Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.Type: ApplicationFiled: April 9, 2019Publication date: October 10, 2019Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Patent number: 10418319Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.Type: GrantFiled: May 14, 2013Date of Patent: September 17, 2019Assignee: Infineon Technologies AGInventors: Oliver Haeberlen, Klaus Schiess, Stefan Kramp
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Publication number: 20190189574Abstract: A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, a semiconductor chip includes a chip front side, a first chip pad located on the chip front side, a second chip pad located on the chip front side and an electrically insulating material located between the first chip pad and the second chip pad, wherein the first chip pad includes a surface layer predominantly comprising copper and the second chip pad includes a surface layer predominantly comprising aluminum.Type: ApplicationFiled: January 30, 2019Publication date: June 20, 2019Inventors: Stefan Kramp, Marco Koitz
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Patent number: 10236265Abstract: A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.Type: GrantFiled: July 28, 2014Date of Patent: March 19, 2019Assignee: Infineon Technologies AGInventors: Stefan Kramp, Marco Koitz
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Patent number: 10018667Abstract: A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.Type: GrantFiled: August 17, 2016Date of Patent: July 10, 2018Assignee: Infineon Technologies AGInventors: Erwin Thalmann, Michael Leutschacher, Christian Musshoff, Stefan Kramp
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Patent number: 9905685Abstract: A semiconductor device includes compensation structures that extend from a first surface into a semiconductor portion. Sections of the semiconductor portion between neighboring ones of the compensation structures form semiconductor mesas. A field dielectric separating a field electrode in the compensation structures from the semiconductor portion includes a thermally grown portion, which directly adjoins the semiconductor portion. A not fully densified deposited portion of the field dielectric has a lower density than the thermally grown portion.Type: GrantFiled: April 27, 2016Date of Patent: February 27, 2018Assignee: Infineon Technologies Austria AGInventors: Ralf Siemieniec, Oliver Blank, Mario Kleindienst, Stefan Kramp
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Patent number: 9786620Abstract: According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.Type: GrantFiled: July 27, 2015Date of Patent: October 10, 2017Assignee: INFINEON TECHNOLGIES AGInventor: Stefan Kramp
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Publication number: 20170033067Abstract: According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.Type: ApplicationFiled: July 27, 2015Publication date: February 2, 2017Inventor: Stefan Kramp
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Publication number: 20160356839Abstract: A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.Type: ApplicationFiled: August 17, 2016Publication date: December 8, 2016Inventors: Erwin Thalmann, Michael Leutschacher, Christian Musshoff, Stefan Kramp