Abstract: A first device receives a first container frame having a payload of a first length. The payload of the container frame includes multiple optical transport unit (OTU) frames, each of which includes an optical data unit (ODU) frame and a sequence of forward error correction (FEC) bits for the ODU frame. Each OTU frame is associated with a first sequence of error-identifying bits. The first device determines, for each OTU frame, a second sequence of error-identifying bits, and forms a second container frame including the OTU frames, the first sequences of error-identifying bits, and the second sequences of error-identifying bits. The first device transmits the second container frame to a second device.

Abstract: In one embodiment an apparatus, method, and system is described, the embodiment an apparatus, method including receiving a stream of data frames at an input interface, the data frames one of including security frames, or being included in security frames, wherein the security frames include payload data, performing forward error correction on the data frames a forward error correction (FEC) decoder, buffering received data frames at a buffer and blanker engine and building a complete security frame of the received data frames, determining whether or not to suppress taking a consequent action based on a frequency of authentication errors at an authentication engine, wherein the consequent action to be taken or suppressed, when taken, is taken upon payload data of one or more security frames including a data frame upon which an authentication error occurred. Related apparatus, methods and systems are also described.

Abstract: A first device receives a first container frame having a payload of a first length. The payload of the container frame includes multiple optical transport unit (OTU) frames, each of which includes an optical data unit (ODU) frame and a sequence of forward error correction (FEC) bits for the ODU frame. Each OTU frame is associated with a first sequence of error-identifying bits. The first device determines, for each OTU frame, a second sequence of error-identifying bits, and forms a second container frame including the OTU frames, the first sequences of error-identifying bits, and the second sequences of error-identifying bits. The first device transmits the second container frame to a second device.

Abstract: A first device receives, over a first communications link, a container frame having a payload of a first length. The payload of the container frame includes multiple optical transport unit (OTU) frames of a second length. The first length is not a multiple of the second length. Each of the OTU frames includes an optical data unit (ODU) frame, a sequence of forward error correction (FEC) bits for the ODU frame, and a sequence of error-identifying bits for the ODU frame. The first device determines, based on the sequences of error-identifying bits, a performance of the first communications link.

Abstract: A first device receives, over a first communications link, a container frame having a payload of a first length. The payload of the container frame includes multiple optical transport unit (OTU) frames of a second length. The first length is not a multiple of the second length. Each of the OTU frames includes an optical data unit (ODU) frame, a sequence of forward error correction (FEC) bits for the ODU frame, and a sequence of error-identifying bits for the ODU frame. The first device determines, based on the sequences of error-identifying bits, a performance of the first communications link.

Abstract: In one embodiment an apparatus, method, and system is described, the embodiment an apparatus, method including receiving a stream of data frames at an input interface, the data frames one of including security frames, or being included in security frames, wherein the security frames include payload data, performing forward error correction on the data frames a forward error correction (FEC) decoder, buffering received data frames at a buffer and blanker engine and building a complete security frame of the received data frames, determining whether or not to suppress taking a consequent action based on a frequency of authentication errors at an authentication engine, wherein the consequent action to be taken or suppressed, when taken, is taken upon payload data of one or more security frames including a data frame upon which an authentication error occurred. Related apparatus, methods and systems are also described.

Abstract: In one embodiment an apparatus, method, and system is described, the embodiment an apparatus, method including receiving a stream of data frames at an input interface, the data frames one of including security frames, or being included in security frames, wherein the security frames include payload data, performing forward error correction on the data frames a forward error correction (FEC) decoder, buffering received data frames at a buffer and blanker engine and building a complete security frame of the received data frames, determining whether or not to suppress taking a consequent action based on a frequency of authentication errors at an authentication engine, wherein the consequent action to be taken or suppressed, when taken, is taken upon payload data of one or more security frames including a data frame upon which an authentication error occurred. Related apparatus, methods and systems are also described.

Abstract: A relay valve is provided for a vehicle. The valve includes a parking brake piston that is displaceable in a housing and an axially displaceable cuff, a first compressed-air chamber for receiving compressed air from a control line is formed between the parking brake piston and the housing. The valve is also provided with a first spring element, which axially applies a pre-loading force to the cuff, and with a second spring element, which axially applies another pre-loading force to the parking brake piston. An axially displaceable service brake piston is arranged axially between the parking brake piston and the cuff, the service brake piston rests at least radially against the parking brake piston and radially against the housing in a sealing manner, in order to form a second compressed-air chamber.

Abstract: In one embodiment an apparatus, method, and system is described, the embodiment an apparatus, method including receiving a stream of data frames at an input interface, the data frames one of including security frames, or being included in security frames, wherein the security frames include payload data, performing forward error correction on the data frames a forward error correction (FEC) decoder, buffering received data frames at a buffer and blanker engine and building a complete security frame of the received data frames, determining whether or not to suppress taking a consequent action based on a frequency of authentication errors at an authentication engine, wherein the consequent action to be taken or suppressed, when taken, is taken upon payload data of one or more security frames including a data frame upon which an authentication error occurred. Related apparatus, methods and systems are also described.

Abstract: A device receives signals over a communication medium and uses a low density parity check decoder to decode data in the signals. A number of unsatisfied parity checks are counted prior to a first decoding iteration of the low density parity check decoder on a basis of log likelihood ratios computed from the signals. An operational characteristic of the low density parity check decoder is computed based on an accumulated number of unsatisfied parity checks.

Abstract: A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

Abstract: A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

Abstract: A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

Abstract: A device receives signals over a communication medium and uses a low density parity check decoder to decode data in the signals. A number of unsatisfied parity checks are counted prior to a first decoding iteration of the low density parity check decoder on a basis of log likelihood ratios computed from the signals. An operational characteristic of the low density parity check decoder is computed based on an accumulated number of unsatisfied parity checks.

Abstract: A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

Abstract: This invention relates to a method and a circuit for estimating the bit error rate in a data transmission system. Symbols are detected (u) by a maximum likelihood detector (1), which provides path metrics of the decoded path and the best competitor at predetermined symbol positions. Absolute path metric differences (2) are calculated between the decoded path and the best competitor at said predetermined symbol positions. Events (5) are counted when an absolute path metric difference (2) is equal to one of a set of difference values. The bit error rate is estimated based on the number of counted (4) events (5). The invention further comprises a method and a circuit in which a function is applied onto said absolute path metric difference. The function maps quantized logarithms of probabilities to probabilities.

Abstract: This invention relates to methods for obtaining a bin number of path metrics. When performing such methods, a histogram is provided, which composes a bin number of values, a maximum value and a tail region left or right of the maximum value. A bin number of path metrics is obtained from said values. According to an embodiment a local extremum is removed from said tail region. According to another embodiment the tail region is forced to be convex. According to a further embodiment a maximum metric difference between neighboring metrics is ensured.

Abstract: This invention relates to methods for obtaining a bin number of path metrics. When performing such methods, a histogram is provided, which comprises a bin number of values, a maximum value and a tail region left or right of the maximum value. A bin number of path metrics is obtained from said values. According to an embodiment a local extremum is removed from said tail region. According to another embodiment the tail region is forced to be convex. According to a further embodiment a maximum metric difference between neighboring metrics is ensured.

Abstract: This invention relates to a method and a circuit for estimating the bit error rate in a data transmission system. Symbols are detected (u) by a maximum likelihood detector (1), which provides path metrics of the decoded path and the best competitor at predetermined symbol positions. Absolute path metric differences (2) are calculated between the decoded path and the best competitor at said predetermined symbol positions. Events (5) are counted when an absolute path metric difference (2) is equal to one of a set of difference values. The bit error rate is estimated based on the number of counted (4) events (5). The invention further comprises a method and a circuit in which a function is applied onto said absolute path metric difference. The function maps quantized logarithms of probabilities to probabilities.

Abstract: This invention relates to methods for obtaining a bin number of path metrics. When performing such methods, a histogram is provided, which comprises a bin number of values, a maximum value and a tail region left or right of the maximum value. A bin number of path metrics is obtained from said values. According to an embodiment a local extremum is removed from said tail region. According to another embodiment the tail region is forced to be convex. According to a further embodiment a maximum metric difference between neighboring metrics is ensured.