Abstract: A multithreaded system includes a processor core having a plurality of hardware threads. One or more of the hardware threads is dedicated to execute only trusted code and the remaining hardware threads are configured to execute untrusted code. The multithreaded system further includes a DLNA (Digital Living Network Alliance) server configured to communicate secure requests to one or more of the hardware threads dedicated to execute only trusted code and communicate other requests to one or more of the remaining hardware threads configured to execute untrusted code.

Abstract: A multithreaded system includes a processor core having a plurality of hardware threads. One or more of the hardware threads is dedicated to execute only trusted code and the remaining hardware threads are configured to execute untrusted code. The multithreaded system further includes a DLNA (Digital Living Network Alliance) server configured to communicate secure requests to one or more of the hardware threads dedicated to execute only trusted code and communicate other requests to one or more of the remaining hardware threads configured to execute untrusted code.

Abstract: A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.

Abstract: A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.

Abstract: In a method and device measuring a delay time of a section of a digital circuit, an output signal of the section is saved in different memory locations with a clock and earlier by a time interval with respect to the clock, different durations being assigned to the time interval. The delay time is determined as a function of the greatest of the different durations during which a test proceeds in a positive manner. The test proceeds in a positive manner if the value saved with the clock corresponds with the value saved so as to be earlier by the corresponding time interval.

Abstract: In a method and device measuring a delay time of a section of a digital circuit, an output signal of the section is saved in different memory locations with a clock and earlier by a time interval with respect to the clock, different durations being assigned to the time interval. The delay time is determined as a function of the greatest of the different durations during which a test proceeds in a positive manner. The test proceeds in a positive manner if the value saved with the clock corresponds with the value saved so as to be earlier by the corresponding time interval.

Abstract: In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being allocated a supply voltage. The hardware description code is transformed into a net list that contains logical cells and their connections. A specific supply voltage is assigned to each cell by a unique identifier. Afterward, a time sequence analysis of the circuit is performed taking account of the identifiers of the cells.

Abstract: In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being allocated a supply voltage. The hardware description code is transformed into a net list that contains logical cells and their connections. A specific supply voltage is assigned to each cell by a unique identifier. Afterward, a time sequence analysis of the circuit is performed taking account of the identifiers of the cells.