Patents by Inventor Stefan Macheiner
Stefan Macheiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862541Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.Type: GrantFiled: July 28, 2021Date of Patent: January 2, 2024Assignee: Infineon Technologies AGInventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
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Publication number: 20230095545Abstract: A semiconductor package includes a leadframe including a diepad and a first row of leads, wherein at least one lead of the first row of leads is physically separated from the diepad by a gap. The semiconductor package further includes a semiconductor component arranged on the leadframe. The semiconductor package further includes an encapsulation material encapsulating the leadframe and the semiconductor component, wherein the encapsulation material includes a bottom surface arranged at a bottom surface of the semiconductor package, a top surface and a side surface extending from the bottom surface to the top surface. A side surface of at least one lead of the first row of leads is flush with the side surface of the encapsulation material. The flush side surface of the at least one lead is covered by an electroplated metal coating.Type: ApplicationFiled: September 22, 2022Publication date: March 30, 2023Inventors: Paul Armand Calo, Thomas Bemmerl, Joo Ming Goa, Edward Myers, Wee Boon Tay, Stefan Macheiner, Markus Dinkel, Andreas Piller
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Patent number: 11569196Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.Type: GrantFiled: August 26, 2021Date of Patent: January 31, 2023Assignee: Infineon Technologies AGInventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
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Patent number: 11469161Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.Type: GrantFiled: August 27, 2020Date of Patent: October 11, 2022Assignee: Infineon Technologies AGInventors: Thorsten Scharf, Chan Lam Cha, Wolfgang Hetzel, Swee Kah Lee, Stefan Macheiner
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Patent number: 11342252Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.Type: GrantFiled: October 6, 2020Date of Patent: May 24, 2022Assignee: Infineon Technologies AGInventors: Stefan Macheiner, Markus Dinkel
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Publication number: 20220068773Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.Type: ApplicationFiled: August 27, 2020Publication date: March 3, 2022Inventors: Thorsten Scharf, Chan Lam Cha, Wolfgang Hetzel, Swee Kah Lee, Stefan Macheiner
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Publication number: 20210391298Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.Type: ApplicationFiled: August 26, 2021Publication date: December 16, 2021Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
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Publication number: 20210358836Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
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Patent number: 11145578Abstract: A package includes a semiconductor die having a first load terminal at a first side and a second load terminal at a second side opposite the first side, a metal block attached to the second load terminal and providing a single primary thermal conduction path of the package, a first metal lead electrically connected to the first load terminal, a second metal lead electrically connected to the second load terminal, and a mold compound embedding the semiconductor die, the metal block, and each metal lead. Each metal lead and the metal block are exposed from the mold compound at a first side of the package. Each metal lead is exposed from the mold compound at a second side of the package opposite the first side, so that the package is configured for surface mounting at either the first side or the second side of the package.Type: GrantFiled: September 24, 2019Date of Patent: October 12, 2021Assignee: Infineon Technologies AGInventor: Stefan Macheiner
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Patent number: 11133281Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.Type: GrantFiled: April 4, 2019Date of Patent: September 28, 2021Assignee: Infineon Technologies AGInventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
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Patent number: 11101201Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.Type: GrantFiled: March 1, 2019Date of Patent: August 24, 2021Assignee: Infineon Technologies AGInventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
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Publication number: 20210090979Abstract: A package includes a semiconductor die having a first load terminal at a first side and a second load terminal at a second side opposite the first side, a metal block attached to the second load terminal and providing a single primary thermal conduction path of the package, a first metal lead electrically connected to the first load terminal, a second metal lead electrically connected to the second load terminal, and a mold compound embedding the semiconductor die, the metal block, and each metal lead. Each metal lead and the metal block are exposed from the mold compound at a first side of the package. Each metal lead is exposed from the mold compound at a second side of the package opposite the first side, so that the package is configured for surface mounting at either the first side or the second side of the package.Type: ApplicationFiled: September 24, 2019Publication date: March 25, 2021Inventor: Stefan Macheiner
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Publication number: 20210020553Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.Type: ApplicationFiled: October 6, 2020Publication date: January 21, 2021Applicant: Infineon Technologies AGInventors: Stefan Macheiner, Markus Dinkel
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Publication number: 20200321276Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.Type: ApplicationFiled: April 4, 2019Publication date: October 8, 2020Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
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Patent number: 10796986Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.Type: GrantFiled: March 21, 2016Date of Patent: October 6, 2020Assignee: Infineon Technologies AGInventors: Stefan Macheiner, Markus Dinkel
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Patent number: 10770399Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.Type: GrantFiled: February 13, 2019Date of Patent: September 8, 2020Assignee: Infineon Technologies AGInventors: Chee Yang Ng, Hock Siang Chua, Stefan Macheiner, Josef Maerz, Nurfarena Othman, Joseph Victor Soosai Prakasam, Hong Hock Tay
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Publication number: 20200279795Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
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Publication number: 20200258842Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Inventors: Chee Yang Ng, Hock Siang Chua, Stefan Macheiner, Josef Maerz, Nurfarena Othman, Joseph Victor Soosai Prakasam, Hong Hock Tay
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Publication number: 20190139869Abstract: A semiconductor package includes a semiconductor die embedded in a molded package body, leads electrically connected to the die and protruding from a side face of the molded package body, and a recess extending inward from the side face and into a bottom main face of the molded package body to form a single groove. The recess begins below a region of the side face from which the leads protrude, so that this region of the side face is flat and each of the leads exits the molded package body in the same plane. A first subset of the leads is bent inward towards the molded package body and seated in the single groove, to form a first row of leads configured for surface mounting. A second subset of the leads extends outward from the molded package body, to form a second row of leads configured for surface mounting.Type: ApplicationFiled: November 7, 2017Publication date: May 9, 2019Inventors: Cher Hau Danny Koh, Hai Sin Chong, Stefan Macheiner, Yong Chern Poh, Toni Salminen, Khay Chwan Saw
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Patent number: 10147703Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.Type: GrantFiled: March 24, 2017Date of Patent: December 4, 2018Assignee: Infineon Technologies AGInventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan