Abstract: Techniques and mechanisms to manage power states for a system-on-chip (SOC). Multiple modules of the SOC include a first module to perform a task including one or more accesses to a memory. In an embodiment, the SOC is transitioned to one of a path-to-memory-available (PMA) power state and a path-to-memory-not-available (PMNA) power state, where the transition is in response to an indication that, of the multiple modules, only the first module is to access the memory during the task. The PMA power state enables data communication between the memory and the first module and prevents data communication between the memory and any other module of the multiple modules. In another embodiment, the PMNA power state prevents data communication between the memory and any of the multiple modules, but allows a low latency transition from the PMNA power state to the PMA power state.

Abstract: For example, a circuit arrangement is provided comprising a clock generator configured to generate a clock signal, a circuit having a low power mode, and a controller, configured to receive, when the circuit is in the low power mode, a request specifying that the circuit should return from the low power mode and trigger the circuit to return from the low power mode when the number of clock cycles of the clock signal since the reception of the request has reached a threshold value.

Abstract: For example, a circuit arrangement is provided comprising a clock generator configured to generate a clock signal, a circuit having a low power mode, and a controller, configured to receive, when the circuit is in the low power mode, a request specifying that the circuit should return from the low power mode and trigger the circuit to return from the low power mode when the number of clock cycles of the clock signal since the reception of the request has reached a threshold value.