Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.

Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.

Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.

Abstract: An apparatus for detecting integrity violation includes a feedback shift register including a plurality of registers connected in series, and a feedback function unit connected between an output of a number of the registers and an input of at least one of the registers. The apparatus further includes an integrity violation detector adapted to determine as to whether a sequence of values at an input or output of at least one of the registers, or a logic combination thereof, is a non-constant sequence or a constant sequence. The apparatus is further adapted to output an indication that the feedback shift register is in an integral state if the sequence of values is a non-constant sequence, or to output an indication that the feedback shift register is subjected to an integrity violation if the sequence of values is a constant sequence.

Abstract: An embodiment relates to a device for a memory access, the device having a first component for conducting operations on the memory and a second component for accessing the memory in a randomized manner, wherein the first component conducts at least a portion of the operations via the second component.

Abstract: A key-generating apparatus is provided for generating a session key which is known to a first communication apparatus and a second communication apparatus, for the first communication apparatus, from secret information which may be determined by the first and second communication apparatuses. The key-generating apparatus includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information, and a second module operable to use the session key for communication with the second communication apparatus.

Abstract: Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a program which includes at least the instruction sequence.

Abstract: A computational system is configured to protect against integrity violation. The computational system includes a processing unit and a critical resource, the critical resource being controllable by the processing unit so as to be locked or unlocked. The critical resource is configured to intermittently transmit a polling value to the processing unit, and the processing unit is configured to apply a transformation onto the polling value so as to obtain a response value and send the response value back to the critical resource. The critical resource is configured to check the response value on correctness so as to obtain a check result, and subject the controllability to a dependency on the check result.

Abstract: An embodiment relates to a device for a memory access, the device comprising a first component for conducting operations on the memory and a second component for accessing the memory in a randomized manner, wherein the first component conducts at least a portion of the operations via the second component.

Abstract: A method for processing an operating sequence of instructions of a program in a processor, wherein each instruction is represented by an assigned instruction code which comprises one execution step to be processed by the processor or a plurality of execution steps to be processed successively by the processor, includes determining an actual signature value assigned to a current execution step of the execution steps of the instruction code representing the instruction of the operating sequence; determining, in a manner dependent on an address value, a desired signature value assigned to the current execution step; and if the actual signature value does not correspond to the desired signature value, omitting at least one execution step directly available for execution and/or an execution step indirectly available for execution.

Abstract: A computational system is configured to protect against integrity violation. The computational system includes a processing unit and a critical resource, the critical resource being controllable by the processing unit so as to be locked or unlocked. The critical resource is configured to intermittently transmit a polling value to the processing unit, and the processing unit is configured to apply a transformation onto the polling value so as to obtain a response value and send the response value back to the critical resource. The critical resource is configured to check the response value on correctness so as to obtain a check result, and subject the controllability to a dependency on the check result.

Abstract: An apparatus includes a pair of an alarm condition generator and an associated alarm circuit and a test circuit. The alarm circuit is configured to generate an alarm signal in response to a detection of an associated alarm condition. The alarm condition generator is configured to generate the associated alarm condition for its associated alarm circuit in response to a reception of a first reset of a first type of reset. The test circuit is configured to receive the alarm signal and the first reset and to generate in response to a reception of both the first reset and the alarm signal a second reset of a second type of reset.

Abstract: An NLFSR of length k, configured to output a sequence of masked values x?i=xi+mi according to a masked recurrence x?n+k=f(x?n, . . . , x?n+k?1), the NLFSR including a nonlinear feedback function configured to compute f(x?n, . . . , x?n+k?1) so as to obtain a feedback value, a correction function configured to compute (mn, . . . , nn+k?1)+mn+k+h(mn, mn+k?1, xn, . . . , xn+k?1) to obtain a correction value c, and a corrector configured to correct the feedback value {circumflex over (x)}?n+k using the correction value c to obtain a corrected feedback value which forms x?n+k.

Abstract: An apparatus for detecting integrity violation includes a feedback shift register including a plurality of registers connected in series, and a feedback function unit connected between an output of a number of the registers and an input of at least one of the registers. The apparatus further includes an integrity violation detector adapted to determine as to whether a sequence of values at an input or output of at least one of the registers, or a logic combination thereof, is a non-constant sequence or a constant sequence. The apparatus is further adapted to output an indication that the feedback shift register is in an integral state if the sequence of values is a non-constant sequence, or to output an indication that the feedback shift register is subjected to an integrity violation if the sequence of values is a constant sequence.

Abstract: An apparatus includes a pair of an alarm condition generator and an associated alarm circuit and a test circuit. The alarm circuit is configured to generate an alarm signal in response to a detection of an associated alarm condition. The alarm condition generator is configured to generate the associated alarm condition for its associated alarm circuit in response to a reception of a first reset of a first type of reset. The test circuit is configured to receive the alarm signal and the first reset and to generate in response to a reception of both the first reset and the alarm signal a second reset of a second type of reset.

Abstract: A device for generating a session key which is known to a first communication partner and a second communication partner, for the first communication partner, from secret information which may be determined by the first and second communication partners, includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information. The device also includes a second module operable to use the session key for communication with the second communication partner.

Abstract: A key-generating apparatus is provided for generating a session key which is known to a first communication apparatus and a second communication apparatus, for the first communication apparatus, from secret information which may be determined by the first and second communication apparatuses. The key-generating apparatus includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information, and a second module operable to use the session key for communication with the second communication apparatus.

Abstract: An instruction decryption arrangement includes an input interface configured to receive an encrypted instruction, a decryption key updater configured to output a decryption key, and an instruction decrypter including a first input connected to the input interface and a second input connected to the decryption key updater, and configured to decrypt the encrypted instruction using the decryption key and to provide a decrypted instruction. The decryption key updater is further configured to update the decryption key using at least one of the encrypted instruction and the decrypted instruction. An alternative instruction decryption arrangement includes a key stream module configured to iteratively determine a key state corresponding to a current instruction for a computing unit and an instruction decrypter configured to receive an encrypted instruction related to the current instruction and decrypt the encrypted instruction using the key state to provide a decrypted instruction.

Abstract: A device for generating a session key which is known to a first communication partner and a second communication partner, for the first communication partner, from secret information which may be determined by the first and second communication partners, includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information. The device also includes a second module operable to use the session key for communication with the second communication partner.

Abstract: A compiler module for providing instruction signature support to a compiler includes a language construct identifier and a placeholder insertion component. The language construct identifier is configured to identify an instruction signature-relevant language construct in a high level language source code supplied to the compiler. The placeholder insertion component is configured to interact with the compiler for inserting at least one instruction signature-related placeholder based on the instruction signature-related language construct into a compiled code processed by the compiler on the basis of the high level language source code.