Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

Abstract: According to one embodiment, a timing circuit (300) can include a first control circuit (302), a first clocked circuit (304), a second clocked circuit (306), and a second control circuit (314). A first control circuit (302) may compensate for a first timing signal FCLK making a transition earlier in time than a second timing signal RCLK. A second control circuit (314) may compensate for a second timing signal RCLK making a transition earlier in time than a first timing signal FCLK. A first timing signal FCLK can be a periodic signal generated by a first PLL type circuit (310) in response to a falling edge of an external clock signal EXT CLK. A second timing signal RCLK can be a periodic signal generated by a second PLL type circuit (312) in response to a rising edge of an external clock signal EXT CLK.

Abstract: According to one embodiment, a content addressable memory (CAM) (100) can include a number of ordinary rows (102-0 to 102-n) that provide ordinary match indications (Match0 to Matchn) as well as redundant rows (108-0 and 108-1) that can provide redundant match indications (RMatch0 and RMatch1). If an ordinary row (102-0 to 102-n) is defective, a redundancy multiplexer (114-0 to 114-n) can be switched to provide a redundant match indication (RMatch0 and RMatch1) as an input to a priority encoder (118) instead of the ordinary match indication from the defective ordinary row.

Abstract: In a single ended simplex dual port memory cell, one port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Abstract: A content addressable memory (CAM) (100) can include a number of CAM entries (102-0 to 102-n). Match indications from CAM entries (102-0 to 102-n) and mismatch indications from complementing circuits (106-0 and 106-n) can be supplied to a switching circuit (108). Mismatch indications can indicate if an entry mismatches data when compared with a comparand (104). In one mode of operation, a switching circuit (108) can provide match indications on a number of switch outputs (SW0 to SWn). In another mode of operation, switching circuit (108) can provide mismatch indications on a number of switch outputs (SW0 to SWn).

Abstract: According to one embodiment, the write circuitry of a content addressable memory (CAM) can include periphery circuits (102) that generate data signals (112) and write control signals (118) that connect over some distance to CAM core circuits (104). CAM core circuits (104) may include bitline write driver circuits (106), a write control circuit (108), and CAM cells (110). Write control signals (118) may include a signal surrounded by its complements and be positioned such that a routing of the write control signal is as long as the longest of the data signals (112).

Abstract: According to one embodiment, a content addressable memory (CAM) (100) can include a number of CAM entries (102-0 to 102-n) and corresponding status stores (106-0 and 106-n). Match indications from the CAM entries (102-0 to 102-n) and status information from status stores (106-0 and 106-n) can be supplied to a switching circuit (108). Status information can indicate if an entry stores valid or invalid data. In one mode of operation, the switching circuit (108) can provide match indication values on a number of switch outputs (SW0 to SWn). In another mode of operation, the switching circuit (108) can provide status information on a number of switch outputs (SW0 to SWn).

Abstract: According to one embodiment, a content addressable memory (CAM) can include at least one match line (404), series-coupled transistor pairs comprising match transistors (402-0 to 402-n) and switch devices (422-0 to 422-n), bit match indicator signals (406-0 to 406-n), mask cell value signals (412-0 to 412-n), a match line precharge limiting device (414), a match line precharge control device (416) and an amplifier circuit (432). This configuration can allow for the regulation of the match line (404) discharge path through a discharge control device (410) and a match indication feedback device (426). This, in turn, can allow for match line (404) precharging while at least one of the bit match indicator signals (406-0 to 406-n) is in an intermediate, or approximately half-VDD, level that is consistent with relatively low power precharging of the applied comparands.

Abstract: A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Abstract: According to one embodiment a content addressable memory (CAM) (100) can segment comparand values and data values into portions. Comparand value portions are compared with corresponding data value portions in sequential compare operations. Sequential compare operations can distribute current peaks over two or more compare operations, thereby reducing peak current transients.

Abstract: According to one embodiment, a multiple signal detect circuit (100) can include a detect node (102) and a reference node (104). The potential of the detect node (102) can be discharged (or charged) at a rate that depends upon the number of active input signals (M1 to Mn). The potential of the reference node (104) can be discharged (or charged) at a reference rate. The reference rate can be greater than the rate at which the detect node (102) is discharged (or charged) when one input signal is activated, and less than the rate at which the detect node (102) is discharged (or charged) when two input signals are activated. A differential voltage between the detect node (102) and reference node (104) can be amplified by an amplifier (110).

Abstract: A method of reading the contents of a dual port memory cell which has a Beta Ratio less than 1.5 is described. A wordline is associated with a selected port of the memory cell. The wordline is coupled to a gate device of the memory cell for controlling communication between the memory cell and a bitline. The gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage. The second conductance is less than the first conductance. A port of the cell is selected by applying a select voltage to the associated wordline. The select voltage is approximately the same as the second wordline voltage. The cell contents are then retrieved from the bitline.

Abstract: A single ended dual port memory cell is described. A bit of data received from one of the first and second ports can be stored. Each of the first and second ports can simultaneously detect the stored bit.A method of reading the contents of a dual port memory cell which has a Beta Ratio less than 1.5 is also described. A wordline is associated with a selected port of the memory cell. The wordline is coupled to a gate device of the memory cell for controlling communication between the memory cell and a bitline. The gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage. The second conductance is less than the first conductance. A port of the cell is selected by applying a select voltage to the associated wordline. The select voltage is approximately the same as the second wordline voltage. The cell contents are then retrieved from the bitline.

Abstract: A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Abstract: An asynchronous flag generator for generating an asynchronous flag having a minimum defined active pulse length. The asynchronous flag generator comprises an arbitrary length flag generator for generating an arbitrary length status flag signal from at least two asynchronous signals, one being a set flag signal and the other being a clear flag signal. A minimum pulse generator for generating a minimum pulse having a predefined pulse length upon initiation of the set flag signal. Combinational logic combines the arbitrary length status flag with the minimum pulse to generate an asynchronous status flag with a defined minimum active pulse length.

Abstract: A FIFO (First-In-First-Out) memory includes a main memory array and a main select circuit having a plurality of serially coupled shift registers, each selecting at least one memory location of the main memory array. The FIFO memory also includes a redundant memory array and a redundant select circuit having a plurality of redundant shift registers, each selecting at least one redundant memory location of the redundant memory array. A switching circuit is provided in the FIFO memory that is coupled to each of the shift registers and each of the redundant shift registers. When a memory location of the main memory is found defective, the switching circuit causes a corresponding shift register of the shift registers to be bypassed in the main select circuit and a redundant shift register of the redundant shift registers to be serially coupled into the main select circuit via a last one of the shift registers.

Abstract: A method is described for accessing data in a memory that has a first memory plane and a second memory plane. The method includes the step of sending a first plurality of data from the first memory plane to a data port. A second plurality of data from the second memory plane is pre-fetched only while the first plurality of data is sent from the first memory plane. The pre-fetching is performed a first plurality of clock cycles before the second plurality of data is sent to the data port.