Abstract: A processor unit can be used to rapidly search a string of characters. The processor unit can include vector registers each having M vector elements, each vector element having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each diagonal of the matrix of comparators, and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. Correction logic within the processor unit can suppress indications of a partial match or of a full match in the bit vector.

Abstract: A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.

Abstract: A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.

Abstract: A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.

Abstract: A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.

Abstract: A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.

Abstract: A memory array includes m·(n+1) memory cells, wherein n and m are natural numbers greater than zero. Each of the plurality of memory cells is connected to one of (n+1) bitlines and one of m wordlines. The memory array further includes n outputs configured for reading a content of the memory array. The memory array further includes n output switches, wherein an i-th output switch is configured for selectively connecting, in response to a switching signal, either an i-th bitline or an (i+1)-th bitline to an i-th output, and wherein i is a natural number and 0?i?n?1. The memory array further includes an (n+1)-th output switch, wherein the (n+1)-th output switch is configured for selectively connecting, in response to the switching signal, either the (n+1)-th bitline or a defined potential to an (n+1)-th output.

Abstract: A memory cell that is readable through a bit line and addressable through a word line can be stressed using a method that includes addressing the memory cell, through the word line, for an addressing time. The memory cell can be stressed by applying a stress voltage to the bit line for a stress voltage time that overlaps with the addressing time for a stress time ?t. A method for testing a memory cell can include writing a data value into the memory cell, stressing the memory cell, reading a stored value from the memory cell and determining whether the stored value corresponds to the data value. A testable memory array can include at least one memory cell that is addressable through a word line and readable through a bit line and a stress circuit for applying a stress voltage to the bit line.

Abstract: A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data.

Abstract: A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data.

Abstract: A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array.

Abstract: A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array.