Abstract: Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.

Abstract: A hierarchical cache system comprises first and second pluralities of data caches and first and second respective higher level caches. The first higher level cache is coupled to the first plurality of caches and stores data of the first plurality of caches. The second higher level cache is coupled to the second plurality of caches and stores data of the second plurality of caches. First and second storage controllers access first and second respective address ranges from a main memory and the higher level cache subsystems. The first higher level cache responds to a request for data not contained in the first higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range.