Abstract: A microprocessor system includes a processing circuit and a memory operably coupled to the processing circuit and configured to receive input data according to a pack and store operation and output the data according to a load and unpack operation. The processing circuit comprises a hardware extension configured to: configure a variable number of bits per data element during a pack and store operation; store a concatenation of a plurality of data elements with a reduced number of bits; extract a plurality of data elements with a reduced number of bits during a load and unpacking operation; and recreate a plurality of data elements with an increased number of bits per data element representative of the data elements prior to the pack and store operation.

Abstract: A Viterbi traceback processing method, system, and apparatus are provided wherein a first Viterbi traceback processing operation (MUX 514) is performed on a first survivor path metric (TMV1) by selecting, in response to a back track state (INDEX 0), a first output data bit (Ti1) for the first survivor path metric, wherein a plurality of Viterbi traceback processing operations (MUX 512, 513) are performed on respective portions of an additional survivor path metric (TMV2A, TMV2B) by selecting, in response to a shifted back track state (INDEX 1), candidate data bits (Tn1, Tn2) for the additional survivor path metric, wherein a multiplexer (MUX 518) controlled by the first output data bit selects between the candidate data bits to generate an additional output data bit (Ti2) for the additional survivor path metric such that the Viterbi traceback processing operations are performed in parallel to produce the output data bits.

Abstract: Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.

Abstract: Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.

Abstract: A microprocessor system (300) is described. The microprocessor system (300) includes a processing circuit (302); and a memory (304), operably coupled to the processing circuit (302) and configured to receive input data according to a pack and store operation and output the data according to a load and unpack operation. The processing circuit (302) comprises a hardware extension (303) configured to: configure a variable number of bits per data element during a pack and store operation; store a concatenation of a plurality of data elements with a reduced number of bits; extract a plurality of data elements with a reduced number of bits during a load and unpacking operation; and recreate a plurality of data elements with an increased number of bits per data element representative of the data elements prior to the pack and store operation.