Abstract: The invention relates to a reference voltage source including a bipolar transistor having a base, a collector and an emitter electrode. The reference voltage source further comprises a Schottky diode (D) whose anode is connected to the base electrode of the bipolar transistor and whose cathode is connected to the collector electrode of the bipolar transistor. The currents flowing through the Schottky diode and bipolar transistor are each set so that a temperature-independent reference voltage (VREF) materializes at the collector electrode of the bipolar transistor.

Abstract: A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.

Abstract: The circuit configuration for the generation of a reference voltage (Vref) contains a reference voltage source (12) and a storage capacitor (C2) to which a voltage provided by a reference voltage source (12) can be applied via a controllable switch. The charging voltage of this storage capacitor (C1) is the reference voltage to be generated. The controllable switch (P1) is a MOS field-effect transistor with back gate (24) which, by means of a refresh signal supplied by a control circuit (22), can be put periodically into either a conducting or a non-conducting state. The back gate (24) of the MOS fieldeffect transistor (P1) is connected to an auxiliary storage capacitor (C2) to which the voltage supplied by the reference voltage source (12) can be applied via a further switch, consisting of a MOS field-effect transistor (P2) with back gate (26), and which is also controlled by the refresh signal.