Abstract: A method, device, and computer program product related to the field of image encoding. In particular, the method, device, and computer program product uses multiple image sensors and multiple encoders for outputting a single encoded image, where image data captured by a first image sensor is added to the encoded image as a first tile or slice, and where image data captured by a second image sensor is added to the encoded image as a second tile or slice.

Abstract: A method, device, and computer program product related to the field of image encoding. In particular, the method, device, and computer program product uses multiple image sensors and multiple encoders for outputting a single encoded image, where image data captured by a first image sensor is added to the encoded image as a first tile or slice, and where image data captured by a second image sensor is added to the encoded image as a second tile or slice.

Abstract: A memory channel means transferring data streams between different blocks and an internal memory means on a data chip, wherein said memory channel means comprises several memory channels. Each channel has source and destination data stream interfaces, wherein each interface is connectable to different blocks, and a flexible address generator generating source and destination addresses for the internal memory means, wherein the order of the data being transferred is changed.

Abstract: A memory channel means transferring data streams between different blocks and an internal memory means on a data chip, wherein said memory channel means comprises several memory channels. Each channel has source and destination data stream interfaces, wherein each interface is connectable to different blocks, and a flexible address generator generating source and destination addresses for the internal memory means, wherein the order of the data being transferred is changed.

Abstract: A method and a multiprotocol network CD-ROM server for providing computer network users possibility to share information on CD-ROM, regardless of other file servers and their locations. The CD-ROM server is a self contained piece of hardware. It provides users connected to different computer networks, using various network protocols, shared access to information of any CD-ROM disc inserted into a connected CD-ROM drive.

Abstract: A digital memory management system for providing access to a digital memory (20) from at least one program process executing in an operating system for at least one digital processor has at least one memory management object (30; 50, 60) with a mapping structure (32a, 32b) for mapping a plurality of physically non-contiguous memory segments (22a, 22b) into a logically contiguous memory block. A reference (41) to an owner (40; 40a, 40b) is given to each physically non-contiguous memory segment. Furthermore, at least one method is arranged for providing random access for the program processes to the logically contiguous memory block, and at least one memory reference handling method is arranged for monitoring the number of references from the program processes to each respective physically non-contiguous memory segments and is arranged to release any of the physically non-contiguous memory segments, when or if it is found not to be in use by any of the program processes.

Abstract: An on-chip i/o-processor for controlling and communication with peripheral devices, wherein an i/o processor core (12), comprising at least one pin controller (29) for reading and setting physical i/o-pins (6), starting timers and generating interrupts for the i/o processor core (12), at least one timer (26) for sampling i/o-pins (6), setting i/o-pins (6) and generating interrupts for the i/o-processor core (12) at well defined points of time, said i/o-processor core (12) providing instructions for controlling said at least one pin controller (29), said at least one timer (26) and i/o-pins (6), an on chip RAM (3) holding instructions for the i/o processor core (12), at least one register (4) for exchanging information between the i/o-processor (2) and a connected CPU (1) on the same chip and inversely, configurable logic (5), connected between said core (12) and said i/o-pins (6), for synchronization of incoming and/or outgoing signals.