Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.

Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.

Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.

Abstract: A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.

Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored n a trap address register.

Abstract: A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.

Abstract: A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.

Abstract: Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Abstract: A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.

Abstract: The invention relates to a reading method of a non-volatile electronic device of the multilevel type, the device comprises at least one first and one second memory bank each of said memory banks comprises a plurality of transistor cells organized in a matrix with a plurality of rows or wordlines and a plurality of columns or bitlines, at least one of said transistor cells being a reference cell containing a reference value, said bitlines being connected to at least one group of sense amplifiers, which comprises in turn a reference terminal and at least one signal output. A crossed electric connection is provided between the reference terminal of at least one group of sense amplifiers of the first memory bank to an output of a subgroup of sense amplifiers of the second memory bank, and vice versa, and the subgroup of sense amplifiers associated with a memory bank is used as a connection to said reference cell during the reading step of the other memory bank.

Abstract: Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Abstract: A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase.

Abstract: A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

Abstract: A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

Abstract: A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

Abstract: A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase.

Abstract: A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

Abstract: A method and a device are provided for reducing the average access time of a non-volatile memory during the reading phase. Reading is effected in either a page mode or a burst mode from a matrix array of memory cells to which recognition logic for recognizing access addresses to the memory is coupled. According to the method, there is provided a buffer memory that is coupled to the matrix array, and a predetermined number of memory words are stored in the buffer memory subsequent to a last-effected reading of the matrix array.