Abstract: A memory cell reconfiguration process is performed in accordance with the operational characteristic settings determined based upon the results of analysis and/or testing of memory cell operations. The memory circuit can include a plurality of memory cells and memory cell configuration controller. The memory cells store information associated with a variety of operations. The memory cell configuration controller coordinates selective enablement and disablement of each of the plurality of memory cells, which can be done on a subset or group basis (e.g., enables and/or disables memory cells on a word length or row by row basis). The address mapping can be adjusted so that the memory space appears continuous to external components. The memory cell configuration controller can also forward configuration information to upstream and/or downstream components that can adjust operations to compensate for the memory cell configuration (e.g., to prevent overflow).

Abstract: Element processors (PE00 to PE33) included in a processor array (7) store pixel values of a search window, shifting them forward. Further, only hatched element processors (PE00, PE02, PE11, PE13, PE20, PE22, PE31, PE33) store pixel values of a template block, and compare them with the pixel values in the search to evaluate a similarity of pixel values. In other words, the pixel values of the template block are skipped and the pixel values which are left after skipping are compared. Therefore, it is possible to cut a hardware volume.

Abstract: The motion vector detecting device with a self-testing function includes an operation circuit that calculates, by block matching, estimation values between a template block and respective image blocks in a search area, an input circuit including a select circuit that selects either data for testing or data being processed, for application to the operation circuit, a comparing circuit that detects, when the data being processed is supplied to the operation circuit, a motion vector of the template block based on the calculated results of the operation circuit, an operation result compressing circuit that performs, when the data for testing is applied to the operation circuit, a predetermined operation on the calculated results of the operation circuit to compress the results for outputting; and a test control circuit that controls data selection of the select circuit.