Patents by Inventor Stefan Slesazeck

Stefan Slesazeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210202752
    Abstract: One example provides an integrated circuit comprising a transistor including a semiconductor channel. The semiconductor channel includes three or more sub-channels, one or more nodes, each node being a junction of at least three sub-channels, and channel ends. A Schottky contact at each channel end forms a source or drain contact, and a gate contact disposed at each Schottky contact controls a barrier conductivity of the corresponding Schottky contact.
    Type: Application
    Filed: December 23, 2020
    Publication date: July 1, 2021
    Applicant: NaMLab gGmbH
    Inventors: Maik Simon, Jens Trommer, Walter Weber, Stefan Slesazeck
  • Patent number: 10963776
    Abstract: An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 30, 2021
    Assignee: NaMLab gGmbH
    Inventors: Halid Mulaosmanovic, Stefan Slesazeck
  • Publication number: 20200357453
    Abstract: One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.
    Type: Application
    Filed: February 5, 2020
    Publication date: November 12, 2020
    Applicant: NaMLab gGmbH
    Inventors: Stefan Slesazeck, Milan Pesic
  • Publication number: 20200065647
    Abstract: An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.
    Type: Application
    Filed: August 26, 2019
    Publication date: February 27, 2020
    Applicant: NaMLab gGmbH
    Inventors: Halid Mulaosmanovic, Stefan Slesazeck
  • Patent number: 10424379
    Abstract: A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 24, 2019
    Assignee: NaMLab gGmbH
    Inventors: Stefan Slesazeck, Halid Mulaosmanovic, Evelyn Breyer
  • Publication number: 20190172539
    Abstract: A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Applicant: NaMLab gGmbH
    Inventors: Stefan Slesazeck, Halid Mulaosmanovic, Evelyn Breyer
  • Patent number: 10043567
    Abstract: An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 7, 2018
    Assignee: NaMLab gGmbH
    Inventors: Stefan Slesazeck, Halid Mulaosmanovic
  • Publication number: 20180082729
    Abstract: An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Inventors: Stefan SLESAZECK, Halid MULAOSMANOVIC
  • Patent number: 9830969
    Abstract: An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: November 28, 2017
    Assignee: NAMLAB GGMBH
    Inventors: Stefan Slesazeck, Halid Mulaosmanovic
  • Publication number: 20170162250
    Abstract: An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 8, 2017
    Inventors: Stefan SLESAZECK, Halid MULAOSMANOVIC
  • Patent number: 8946617
    Abstract: A photodiode comprises a semiconductor material having a p-n junction, the p-n junction being located between a first doping region of a first doping type and a second doping region of a second doping type, the second doping region comprising a highly doped layer and a lightly doped layer. A photodiode further comprises a voltage source being capable to apply a variable voltage between the first doping region and the lightly doped layer of the second doping region in order to vary the expansion of a space charge zone of the p-n junction.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: February 3, 2015
    Assignee: NaMLab gGmbH
    Inventors: Juergen Holz, Andre Wachowiak, Stefan Slesazeck
  • Publication number: 20120286144
    Abstract: A photodiode comprises a semiconductor material having a p-n junction, the p-n junction being located between a first doping region of a first doping type and a second doping region of a second doping type, the second doping region comprising a highly doped layer and a lightly doped layer. A photodiode further comprises a voltage source being capable to apply a variable voltage between the first doping region and the lightly doped layer of the second doping region in order to vary the expansion of a space charge zone of the p-n junction.
    Type: Application
    Filed: November 10, 2011
    Publication date: November 15, 2012
    Applicant: NaMLab GmbH
    Inventors: Juergen Holz, Andre Wachowiak, Stefan Slesazeck
  • Patent number: 7940558
    Abstract: An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: May 10, 2011
    Assignee: Qimonda AG
    Inventor: Stefan Slesazeck
  • Patent number: 7738279
    Abstract: According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: June 15, 2010
    Assignee: Qimonda AG
    Inventors: Stefan Slesazeck, Till Schloesser, Ulrike Gruening-Von Schwerin
  • Patent number: 7719869
    Abstract: A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated with a pair of cell rows. The memory cell array also includes bitlines, wherein each bitline is electrically connected to an individual memory cell of each pair of the cell rows.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: May 18, 2010
    Assignee: Qimonda AG
    Inventor: Stefan Slesazeck
  • Publication number: 20100110753
    Abstract: An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 6, 2010
    Applicant: QIMONDA AG
    Inventors: Stefan Slesazeck, Rolf Weis, Stefan Jakschik
  • Patent number: 7688660
    Abstract: A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: March 30, 2010
    Assignee: Qimonda AG
    Inventor: Stefan Slesazeck
  • Publication number: 20100014372
    Abstract: A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state.
    Type: Application
    Filed: October 2, 2009
    Publication date: January 21, 2010
    Inventor: Stefan Slesazeck
  • Publication number: 20090296449
    Abstract: According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices.
    Type: Application
    Filed: June 2, 2008
    Publication date: December 3, 2009
    Inventors: Stefan Slesazeck, Till Schloesser, Ulrike Gruening Von Schwerin
  • Patent number: 7622354
    Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: November 24, 2009
    Assignee: Qimonda AG
    Inventors: Lars Dreeskornfeld, Jessica Hartwich, Tobias Mono, Arnd Scholz, Stefan Slesazeck