Patents by Inventor Stefan Woetzel

Stefan Woetzel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12283538
    Abstract: A molded semiconductor package includes: a mold compound; a metal substrate partly embedded in the mold compound; at least one first metal lead partly embedded in the mold compound; an inlay embedded in the mold compound, the inlay comprising a semiconductor die embedded in an electrically insulating body, a first metal structure attached to a first side of the semiconductor die, and a second metal structure attached to a second side of the semiconductor die; and a metal clip at least partly embedded in the mold compound and connecting the second metal structure to the at least one first metal lead. The semiconductor die has a maximum junction temperature higher than a glass transition temperature of the mold compound, the electrically insulating body has a glass transition temperature at or above the maximum junction temperature of the semiconductor die, and the metal substrate is attached to the first metal structure.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 22, 2025
    Assignee: Infineon Technologies AG
    Inventors: Marcus Boehm, Michael Fuegl, Ludwig Heitzer, Stefan Woetzel
  • Patent number: 11984392
    Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 14, 2024
    Assignee: Infineon Technologies AG
    Inventors: Chee Yang Ng, Stefan Woetzel, Edward Fuergut, Thai Kee Gan, Chee Hong Lee, Jayaganasan Narayanasamy, Ralf Otremba
  • Publication number: 20230369177
    Abstract: A molded semiconductor package includes: a mold compound; a metal substrate partly embedded in the mold compound; at least one first metal lead partly embedded in the mold compound; an inlay embedded in the mold compound, the inlay comprising a semiconductor die embedded in an electrically insulating body, a first metal structure attached to a first side of the semiconductor die, and a second metal structure attached to a second side of the semiconductor die; and a metal clip at least partly embedded in the mold compound and connecting the second metal structure to the at least one first metal lead. The semiconductor die has a maximum junction temperature higher than a glass transition temperature of the mold compound, the electrically insulating body has a glass transition temperature at or above the maximum junction temperature of the semiconductor die, and the metal substrate is attached to the first metal structure.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventors: Marcus Boehm, Michael Fuegl, Ludwig Heitzer, Stefan Woetzel
  • Patent number: 11710684
    Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: July 25, 2023
    Assignee: Infineon Technologies AG
    Inventors: Frank Singer, Martin Gruber, Thorsten Meyer, Thorsten Scharf, Peter Strobel, Stefan Woetzel
  • Patent number: 11676879
    Abstract: A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 13, 2023
    Assignee: Infineon Technologies AG
    Inventors: Stefan Woetzel, Chee Yang Ng
  • Publication number: 20230052437
    Abstract: A method of producing a semiconductor package includes providing a substrate formed of electrically insulating material and including a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die including a first conductive terminal that faces the die mounting surface, providing a second semiconductor die that includes a first conductive terminal, and mounting the second semiconductor die on the die mounting surface such that the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface, a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed, and the second semiconductor die partially overlaps with the first semiconductor die.
    Type: Application
    Filed: October 26, 2022
    Publication date: February 16, 2023
    Inventors: Stefan Woetzel, Chee Yang Ng
  • Patent number: 11521907
    Abstract: A semiconductor package includes a substrate formed of electrically insulating material and having a die mounting surface, a first semiconductor die embedded within the substrate and comprising a first conductive terminal that faces the die mounting surface, a second semiconductor die mounted on the die mounting surface and comprising a first conductive terminal that faces and is spaced apart from the die mounting surface, and a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together, wherein the second semiconductor die partially overlaps with the first semiconductor die.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: December 6, 2022
    Assignee: Infineon Technologies AG
    Inventors: Stefan Woetzel, Chee Yang Ng
  • Publication number: 20220115287
    Abstract: A semiconductor package includes a substrate formed of electrically insulating material and having a die mounting surface, a first semiconductor die embedded within the substrate and comprising a first conductive terminal that faces the die mounting surface, a second semiconductor die mounted on the die mounting surface and comprising a first conductive terminal that faces and is spaced apart from the die mounting surface, and a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together, wherein the second semiconductor die partially overlaps with the first semiconductor die.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Stefan Woetzel, Chee Yang Ng
  • Publication number: 20220102263
    Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 31, 2022
    Inventors: Chee Yang Ng, Stefan Woetzel, Edward Fuergut, Thai Kee Gan, Chee Hong Lee, Jayaganasan Narayanasamy, Ralf Otremba
  • Publication number: 20220102235
    Abstract: A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Inventors: Stefan Woetzel, Chee Yang Ng
  • Publication number: 20210111108
    Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 15, 2021
    Applicant: Infineon Technologies AG
    Inventors: Frank Singer, Martin Gruber, Thorsten Meyer, Thorsten Scharf, Peter Strobel, Stefan Woetzel