Abstract: A method for synthesizing a clock signal, said clock signal being locked to a reference clock signal, said method providing for using a third clock signal, operating at a higher frequency. The method provides the steps of: measuring the reference clock signal (CK_REF) by means of the third clock signal (CK_HIGH), operating at a higher frequency, obtaining a measured value (MES) of the reference clock signal (CK_REF) frequency; comparing the measured value (MES) with a nominal value; obtaining a correction value (CRR) as a function of the measured value (MES) and storing said correction value (CRR); using said correction value (CRR) for driving a digital controlled oscillator (OC) that outputs the synthesized clock signal (CK_SYN).

Abstract: A system for processing and transmitting a clock signal, in particular the video synchronization frequency Fsr, in order to obtain a binary flow with pre-fixed and desired speed, e.g. a flow at 64 Kb/s. The system can survey the jitter of Fsr and determine its value, using this value to suitably condition the information flow at output. In a typical application, this information, together with a video/audio signal, forms four musical channels and, with low speed, flows to the inputs of a circuit that carries out multiplexing at 34368 Kb/s, according to the European standard. This multiplexer operating at 34368 Kb/s can be advantageously used in systems and equipment for the processing of the television signal using mono or bidimensional transformation coding to obtain a high compression of the information to be transmitted.