Patents by Inventor Stefano Castorina

Stefano Castorina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088790
    Abstract: A control device for a switching voltage regulator having a switching circuit receives a set of measurement signals including a first measurement signal indicative of an output voltage of the switching voltage regulator. A burst-mode controller is configured to monitor the output voltage with respect to a first threshold and a second threshold higher than the first threshold, and to provide, in response, a burst signal. A driving-signal generation stage is configured to provide at least one switching control signal for the switching circuit based on the burst signal and the set of measurement signals. The driving-signal generation stage has a feedback module configured to provide a control signal based on the burst signal and an error signal indicative of a difference between the first measurement signal and a reference signal.
    Type: Application
    Filed: August 17, 2023
    Publication date: March 14, 2024
    Inventors: Ivan Floriani, Stefano Castorina, Giulia Altamura, Emanuele Moretti
  • Publication number: 20240072670
    Abstract: A controller for a buck-boost switching converter, which includes an inductor and a shunt resistor and is coupled to a load which draws a load current, includes a control circuit which performs charge and discharge cycles of the inductor. A first comparator stage generates a first signal which is indicative of a direction of the resistor current during the charge and discharge cycles. A low-pass filtering circuit generates a filtered electrical quantity based on a voltage on the shunt resistor during the charge and discharge cycles. A second comparator stage generates a second signal indicative of a comparison between the filtered electrical quantity and a reference electrical quantity. A detection stage detects the occurrence of an overcurrent in the load based on the second signal.
    Type: Application
    Filed: June 30, 2023
    Publication date: February 29, 2024
    Inventors: Stefano Castorina, Elena Brigo
  • Patent number: 11885845
    Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high-side (HS) or low-side (LS) driver channels. The integrated circuit includes, for each driver channel, a respective on-state test circuit and a respective controller. The on-state test circuits can be selectively configured to test for HS overcurrent conditions, LS overcurrent conditions, HS open load conditions, and LS open load conditions.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: January 30, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Gaudenzia Bagnati, Stefano Castorina, Valerio Bendotti
  • Publication number: 20230421039
    Abstract: Provided is a control device is for a switching voltage regulator having a switching circuit. The control device receives input and output voltages of the switching circuit and a measurement signal indicative of a current of the switching circuit. The control device has: a feedback module that detects an error signal indicative of a difference between the output voltage and a nominal voltage, and provides a control signal as a function of the error signal; a threshold-correction module that provides offset and ramp signals; and a driving-signal generation module coupled to the feedback and threshold-correction modules, which receives the measurement signal, compares the measurement signal with a threshold and, in response, provides a modulated signal for driving the switching circuit. The threshold is a function of the control, offset and ramp signals. The threshold-correction module provides the offset signal as a function of the input or output voltages.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 28, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Stefano CASTORINA, Elena BRIGO, Ivan FLORIANI
  • Patent number: 11789046
    Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 17, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Argento, Orazio Pennisi, Stefano Castorina, Vanni Poletto, Matteo Landini, Andrea Maino
  • Publication number: 20230324475
    Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Inventors: Davide Argento, Orazio Pennisi, Stefano Castorina, Vanni Poletto, Matteo Landini, Andrea Maino
  • Publication number: 20230266382
    Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high-side (HS) or low-side (LS) driver channels. The integrated circuit includes, for each driver channel, a respective on-state test circuit and a respective controller. The on-state test circuits can be selectively configured to test for HS overcurrent conditions, LS overcurrent conditions, HS open load conditions, and LS open load conditions.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Gaudenzia BAGNATI, Stefano CASTORINA, Valerio BENDOTTI
  • Patent number: 11719761
    Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: August 8, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Argento, Orazio Pennisi, Stefano Castorina, Vanni Poletto, Matteo Landini, Andrea Maino
  • Publication number: 20230055745
    Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 23, 2023
    Inventors: Davide Argento, Orazio Pennisi, Stefano Castorina, Vanni Poletto, Matteo Landini, Andrea Maino
  • Publication number: 20230054951
    Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 23, 2023
    Inventors: Davide Argento, Orazio Pennisi, Stefano Castorina, Vanni Poletto, Matteo Landini, Andrea Maino
  • Patent number: 11563319
    Abstract: Disclosed herein is a single integrated circuit chip with a main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. The safety area is internally powered by an internal regulated voltage generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage while protecting against shorts of the external line delivering the external voltage. The safety area includes protection circuits that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits serving to protect against shorts of the external line delivering the external analog signals.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 24, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Cignoli, Nicola Errico, Paolo Vilmercati, Stefano Castorina, Enrico Ferrara