Patents by Inventor Stefano Dal Toso
Stefano Dal Toso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230246635Abstract: It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising: i) a multiplier device (110), configured to receive a single-ended incoming signal (105), and multiply the incoming signal (105) to provide a multiplied signal (115); and ii) a divider device (120), configured to receive the multiplied signal (115), and divide the multiplied signal (115) to provide a differential signal (125a, 125b). Further, a corresponding signal conversion method is described.Type: ApplicationFiled: December 5, 2022Publication date: August 3, 2023Inventors: Stefano Dal Toso, Olivier Susplugas
-
Patent number: 11545982Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (??LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.Type: GrantFiled: March 23, 2022Date of Patent: January 3, 2023Assignee: NXP B.V.Inventors: Mathieu Perin, Stefano Dal Toso, Khurram Waheed, Claudio Gustavo Rey
-
Patent number: 11489532Abstract: An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.Type: GrantFiled: April 27, 2021Date of Patent: November 1, 2022Assignee: NXP B.V.Inventors: Mathieu Périn, Stefano Dal Toso
-
Publication number: 20220321132Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (??LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.Type: ApplicationFiled: March 23, 2022Publication date: October 6, 2022Inventors: Mathieu Perin, Stefano Dal Toso, Khurram Waheed, Claudio Gustavo Rey
-
Publication number: 20220311446Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.Type: ApplicationFiled: March 18, 2022Publication date: September 29, 2022Inventors: Mathieu Perin, Stefano Dal Toso, Khurram Waheed, Claudio Gustavo Rey
-
Patent number: 11437985Abstract: A duty cycle correction circuit (DCCC) for a multi-modulus frequency divider, the DCCC comprising: a corrector chain comprising a plurality of flip-flops each configured to receive one of the internal signals; and at least one delay selection logic element, each configured to receive an output signal from different ones of the flip-flops and the output of each delay selection logic element is based on the received output signal and the division factor; the DCCC is configured such that: a first state change in its output signal is defined by a transition to a first logic state of one of the internal signals; and a second state change in its output signal is based on a transition to a second logic state of one of the internal signals after a delay period, wherein the duty cycle of the output signal is based on the delay period.Type: GrantFiled: October 1, 2021Date of Patent: September 6, 2022Assignee: NXP USA, Inc.Inventors: Mathieu Vallet, Stefano Dal Toso, Mathieu Périn
-
Publication number: 20220263512Abstract: An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.Type: ApplicationFiled: April 27, 2021Publication date: August 18, 2022Inventors: Mathieu Périn, Stefano Dal Toso
-
Patent number: 11196429Abstract: Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.Type: GrantFiled: July 27, 2020Date of Patent: December 7, 2021Assignee: NXP USA, Inc.Inventors: Stefano Dal Toso, Mathieu Perin
-
Patent number: 11114978Abstract: A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus includes a plurality of unit variable reactance structures including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.Type: GrantFiled: October 2, 2020Date of Patent: September 7, 2021Assignee: NXP B.V.Inventors: Mathieu Perin, Stefano Dal Toso
-
Publication number: 20210126584Abstract: A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus comprises includes a plurality of unit variable reactance structures comprising including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals comprising including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator comprises includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method comprises includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.Type: ApplicationFiled: October 2, 2020Publication date: April 29, 2021Inventors: Mathieu Perin, Stefano Dal Toso
-
Patent number: 10951171Abstract: Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.Type: GrantFiled: March 5, 2019Date of Patent: March 16, 2021Assignee: NXP USA, Inc.Inventors: Maicol Cannella, Aurelien Larie, Stefano Dal Toso
-
Publication number: 20210067164Abstract: Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.Type: ApplicationFiled: July 27, 2020Publication date: March 4, 2021Applicant: NXP USA, Inc.Inventors: Stefano Dal Toso, Mathieu Perin
-
Publication number: 20200195199Abstract: Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.Type: ApplicationFiled: March 5, 2019Publication date: June 18, 2020Inventors: Maicol Cannella, Aurelien Larie, Stefano Dal Toso
-
Patent number: 9490745Abstract: A voltage-controlled oscillator comprises a tank circuit and first and second pairs of transistors. Each transistor comprises a gate, a drain, and a source. The drains of the first pair are coupled to the tank circuit and the gates of the first pair are cross-coupled with the drains of the first pair. The drains of the second pair are coupled to the tank circuit and the gates of the second pair are cross-coupled with the drains of the second pair. The oscillator includes a first resonant filter comprising a first terminal coupled to the sources of the first pair and a second resonant filter comprising a first terminal coupled to the sources of the second pair. A method includes adjusting capacitance in a resonant filter to cause the resonant filter to resonate based on a selected frequency.Type: GrantFiled: January 21, 2015Date of Patent: November 8, 2016Assignee: Marvell International Ltd.Inventors: Stefano Dal Toso, Rinaldo Castello, Marco Garampazzi, Paulo Mateus Mendes, Nicola Codega, Danilo Manstretta
-
Patent number: 9000815Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.Type: GrantFiled: March 15, 2013Date of Patent: April 7, 2015Assignee: Marvell World Trade Ltd.Inventors: Luca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
-
Patent number: 8965310Abstract: A transmitter including a first mixer, a first frequency divider to divide a frequency of an input signal to generate a first signal, and a plurality of second frequency dividers to divide the frequency to respectively generate a plurality of second signals, and a control module. In response to the transmitter being turned on, the control module turns on the first frequency divider, turns off the plurality of second frequency dividers, and drives the first mixer with the first signal. Subsequently, in response to determining that a transmit power of the transmitter is to be increased, the control module sequentially turns on and connects each of the plurality of second frequency dividers in parallel to the first frequency divider. Upon a second frequency divider being connected to the first frequency divider, the control module also drives the first mixer using the second signal generated by that second frequency divider.Type: GrantFiled: May 13, 2013Date of Patent: February 24, 2015Assignee: Marvell World Trade Ltd.Inventors: Danilo Gerna, Stefano Dal Toso, Gregory Uehara
-
Publication number: 20130244598Abstract: A transmitter including a first mixer, a first frequency divider to divide a frequency of an input signal to generate a first signal, and a plurality of second frequency dividers to divide the frequency to respectively generate a plurality of second signals, and a control module. In response to the transmitter being turned on, the control module turns on the first frequency divider, turns off the plurality of second frequency dividers, and drives the first mixer with the first signal. Subsequently, in response to determining that a transmit power of the transmitter is to be increased, the control module sequentially turns on and connects each of the plurality of second frequency dividers in parallel to the first frequency divider. Upon a second frequency divider being connected to the first frequency divider, the control module also drives the first mixer using the second signal generated by that second frequency divider.Type: ApplicationFiled: May 13, 2013Publication date: September 19, 2013Applicant: Marvell World Trade Ltd.Inventors: Danilo Gerna, Stefano Dal Toso, Gregory Uehara
-
Patent number: 8442462Abstract: A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of the plurality of second frequency dividers includes a second plurality of components and is configured to divide the input frequency of the input signal to generate a second signal having the first frequency and a second phase. The control module is configured to connect the second plurality of components of one of the second frequency dividers to the first plurality of components of the first frequency divider.Type: GrantFiled: July 29, 2011Date of Patent: May 14, 2013Assignee: Marvell World Trade Ltd.Inventors: Danilo Gerna, Stefano Dal Toso, Gregory Uehara
-
Patent number: 8400197Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.Type: GrantFiled: July 26, 2011Date of Patent: March 19, 2013Assignee: Marvell World Trade Ltd.Inventors: Luca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
-
Publication number: 20120027121Abstract: A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of the plurality of second frequency dividers includes a second plurality of components and is configured to divide the input frequency of the input signal to generate a second signal having the first frequency and a second phase. The control module is configured to connect the second plurality of components of one of the second frequency dividers to the first plurality of components of the first frequency divider.Type: ApplicationFiled: July 29, 2011Publication date: February 2, 2012Inventors: Danilo Gerna, Stefano Dal Toso, Gregory Uehara