Abstract: An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Abstract: An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Abstract: An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Abstract: A new process for the preparation of bicyclic peptide compounds Formula (I) in high yields of high purity, useful as intermediates for preparing compounds with pharmacological activity, is described.

Abstract: An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, connected to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Abstract: An integrated device, including: a first conductive region; a second conductive region set at a distance from the first conductive region; an etch-stop layer, made of a first dielectric material, at least partially overlapped on the first and second conductive regions; an insulating layer, made of a second dielectric material, different from the first, overlapped on the first and second conductive regions and on the etch-stop layer; at least one through opening extending through the insulating layer and the etch-stop layer; and a barrier layer, made of a third dielectric material, different from the first, set between the first conductive region and the etch-stop layer and between the second conductive region and the etch-stop layer.

Abstract: The present invention refers to a pharmaceutical composition for parenteral administration as vaccine comprising a monoclonal antibody and as adjuvant an aluminium derivative.

Abstract: The present invention relates to a new process carried out entirely in solution, for the preparation in high yields of high purity bicyclic peptide compounds of formula (I), useful as intermediates for preparing compounds with pharmacological activity.

Abstract: The present invention refers to a pharmaceutical composition for parenteral administration as vaccine comprising a monoclonal antibody and as adjuvant an aluminium derivative.

Abstract: An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain region formed in the semiconductor material layer. The source and drain regions are spaced apart from each other by a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, the insulated gate extending over the charge carriers drift portion. The drain region is located at a depth compared to the front surface for causing charge carriers to move in the charge carriers drift portion away from an interface between the semiconductor material layer and the gate dielectric.

Abstract: An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain region formed in the semiconductor material layer. The source and drain regions are spaced apart from each other by a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, the insulated gate extending over the charge carriers drift portion. The drain region is located at a depth compared to the front surface for causing charge carriers to move in the charge carriers drift portion away from an interface between the semiconductor material layer and the gate dielectric.

Abstract: Process of preparing (E)-5-(2-bromovynyl)-2?-deoxyuridine (Brivudine) characterized in that halogen-free solvent selected form esters or cyclic ethers are used in the bromination step of 5-ethyl-2?-deoxyuridine diacylate. The use of solvents is advantageous in respect of toxicity, discharge costs and environment protection.

Abstract: Topical formulations containing the virustatic agent brivudine and stabilizers useful to present its photodegradation are disclosed.

Abstract: There is disclosed the use of metal-oxides pigments as photodegradation stabilizers in topical compositions containing brivudine.

Abstract: The present invention relates to the preparation of (E)-5-(2-bromovynyl)-2′-deoxyuridine (Brivudine) characterized in that halogen-free solvents selected form esters or cyclic ethers are used in the bromination step of 5-ethyl-2′deoxyuridine diacy-late. The use of said solvents is advantageous in respect of toxicity, discharge costs and environment protection.

Abstract: High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

Abstract: High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

Abstract: A varactor has a gate region, first and second biasing regions of N+ type embedded in a well, and first and second extraction regions of P+ type, forming a pair of PN junctions with the well. The PN junctions are inversely biased and extract charge accumulating in the well, below the gate region, when the gate region is biased to a lower voltage than a predetermined threshold value.

Abstract: The present invention refers to tachykinins antagonists of general formula (I) ##STR1## their preparation and pharmaceutical compositions containing them.

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.