Abstract: A voltage translator circuit for driving the rows or wordlines of Flash EEPROM memories, having control logic voltages in the range 0 to 3.3 volts, as well as operating voltages needed for reading, programming or erasing operations in the range −9 to 12 volts. The voltage translator circuit includes a first feedback transistor (TP4), the gate of which (node 18) is directly driven by the wordline, and a second feedback transistor (TN5), the gate of which is also driven by the wordline (node 18), inserted between the connection node (node 6) between the first feedback transistor (TP4) and the gate region of a first switch transistor (pull-up 3) and the input node (node 0) on the gate region of a second switch transistor (pull-down 2).

Abstract: A voltage multiplier circuit or charge pump circuit for CMOS integrated circuits having high power efficiency, high current drive and efficient area utilization. An embodiment comprises two mirrored sections driven by control signals (PH00, PH01, PH0.sub.-- P; PH10, PH11, PH1.sub.-- P) generated by a logic circuitry which receives, as input signals, an enable signal (en) and a clock signal (clk), wherein each mirrored section includes N stages and each stage comprises a capacitor (C00, C01, C02; C10, C11, C12) having a lower terminal and an upper terminal, the lower terminal is connected to a first switch (INV0, NCH00, NCH01; INV1, NCH10, NCH11) that, in closed condition, couples the lower terminal of the capacitor to ground (GND), said lower terminal of the capacitor being additionally connected to a second switch (INV0, PCH00, PCH01; INV1, PCH10, PCH11) that, in closed condition, couples the lower terminal of the capacitor to the supply voltage (Vpp).

Abstract: A field memory having a distributed architecture is disclosed and in particular a memory arranged in block, wherein each block stores a bit or bits of said word, said bits having a predetermined position within said word. The distributed architecture improves the transfer of data between the input/output buffers and the internal registers of the memory. A data cache and an improved input erasable realisation are also disclosed.

Abstract: A voltage multiplier has two mirrored sections which are clocked by nonoverlapping phases. Each section of the voltage multiplier has N stages: each stage is made of a capacitor and MOS transistors operating as switches. During a charging phase, the N capacitors are insulated from each other and the terminals of each capacitor are connected one to voltage Vpp and the other to ground GND by means of PMOS transistors. During the discharge phase, the N capacitors are connected in series, with the bottom plate of the first stage capacitor coupled to ground voltage GND and the top plate of the last-but-one stage capacitor coupled to the output through a PMOS transistor. The gate voltage of this PMOS transistor is furnished by the last stage, in the upper portion of the circuit, in order to drive the transistor into a fully on condition.

Abstract: An on-chip voitage multiplier circuit, comprising N serially arranged stages wherein each stage includes a switch Tj (j=1 . . . N), having an upper pin and a lower pin, to the upper pin of which the lower pin of a capacitor Ci (i=1 . . . N) is serially connected, said capacitor also having a lower pin and an upper pin; the intermediate node between each switch Tj (j=1 . . . N) and each capacitor Ci (i=1 . . . N) is connected to the ground voltage Vss through a respective switch Si (i=1 . . . N) and the upper pin of each capacitor Ci (i=1 . . . N) is connected to the supply voltage Vdd through a switch Di (i=1 . . . N); and the lower pin of the switch (T11) of the first stage is directly connected to the supply voltage Vdd and the upper pin of the capacitor (CN) of the last stage is connected to the output pin through an additional switch (T(N+1)).