Patents by Inventor Stefano Pellerano
Stefano Pellerano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956104Abstract: Millimeter-wave (mmWave) and sub-mmWave technology, apparatuses, and methods that relate to transceivers and receivers for wireless communications are described. The various aspects include an apparatus of a communication device including one or more antennas configured to receive an RF signal and an ADC system. The ADC system includes a 1-bit ADC configured to receive the RF signal, and an ADC controller circuitry configured to measure a number of positive samples in the received RF signal for a plurality of thresholds of the 1-bit ADC, estimate receive signal power associated with the received RF signal based on the measured number of positive samples, determine a direct current (DC) offset in the received RF signal using the estimated received signal power, and adjust the received RF signal based on the determined DC offset.Type: GrantFiled: December 26, 2019Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Oner Orhan, Hosein Nikopour, Mehnaz Rahman, Ivan Simoes Gaspar, Shilpa Talwar, Stefano Pellerano, Claudio Da Silva, Namyoon Lee, Yo Seb Jeon, Eren Sasoglu
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Patent number: 11955965Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.Type: GrantFiled: May 27, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Sushil Subramanian, Stefano Pellerano, Todor Mladenov, JongSeok Park, Bishnu Prasad Patra
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Patent number: 11955732Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.Type: GrantFiled: December 27, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
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Publication number: 20240097693Abstract: An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Somnath KUNDU, Amy L. WHITCOMBE, Stefano PELLERANO, Peter SAGAZIO, Brent CARLTON
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Patent number: 11923809Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. An output passive network can further generate a flat-phase response between dual resonances of operation.Type: GrantFiled: August 22, 2022Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull
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Patent number: 11916604Abstract: Embodiments may relate to a communications module comprising with a dispersion compensation module communicatively coupled between a baseband module and a radio frequency (RF) module. The dispersion compensation module may be configured to process a data signal at an intermediate frequency that is between a baseband frequency and a RF frequency. Other embodiments may be described or claimed.Type: GrantFiled: June 5, 2020Date of Patent: February 27, 2024Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu Gaunkar, Telesphor Kamgaing, Thomas W. Brown, Stefano Pellerano
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Publication number: 20240021522Abstract: Various devices, systems, and/or methods perform wireless chip to chip high speed data transmission. Strategies for such transmission include use of improved microbump antennas, wireless chip to chip interconnects, precoding and decoding strategies, channel design to achieve spatial multiplexing gain in line of sight transmissions, open cavity chip design for improved transmission, and/or mixed signal channel equalization.Type: ApplicationFiled: December 23, 2020Publication date: January 18, 2024Inventors: Tolga ACIKALIN, Tae Young YANG, Debabani CHOUDHURY, Shuhei YAMADA, Roya DOOSTNEJAD, Hosein NIKOPOUR, Issy KIPNIS, Oner ORHAN, Mehnaz RAHMAN, Kenneth P. FOUST, Christopher D. HULL, Telesphor KAMGAING, Omkar KARHADE, Stefano PELLERANO, Peter SAGAZIO, Sai VADLAMANI
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Publication number: 20240022248Abstract: Apparatus and methods for interfacing an integrated qubit control chip and a solid state qubit; detecting a qubit state with a transition pulse histogram; high resolution and high speed rectangular pulse generation; large-scale spin qubit state readout; and activity-based clock control.Type: ApplicationFiled: September 25, 2020Publication date: January 18, 2024Inventors: Stefano PELLERANO, Christopher HULL, Todor MLADENOV, JongSeok PARK, Ilya KLOCHKOV, Sushil SUBRAMANIAN
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Publication number: 20230320237Abstract: Technologies for scalable spin qubit readout are disclosed. In the illustrative embodiment, superconducting and semiconducting components are integrated onto a single chip, allowing for frequency and temporal multiplexing components to be integrated onto the same die. The semiconducting components on the die can include transistors, varactors, and amplifiers, and the superconducting components can include an inductor and a capacitor that form part of an impedance matching network.Type: ApplicationFiled: March 15, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Bishnu Prasad Patra, Stefano Pellerano, JongSeok Park
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Publication number: 20230291433Abstract: A transceiver may include a transmit path and a receive path that are each coupled to a radio frequency (RF) interface, and a self-interference canceller (SIC). The SIC is coupled between the transmit and the receive paths. The SIC is configured to cancel a self-interference signal from a received signal on the receive path based on a transmit signal on the transmit path.Type: ApplicationFiled: June 25, 2021Publication date: September 14, 2023Inventors: Ofer Benjamin, Eli Borokhovich, Brent Carlton, Ofir Degani, Ronen Kronfeld, Stefano Pellerano, Mustafijur Rahman, Ehud Reshef, Sarit Zur
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Publication number: 20230210023Abstract: Technologies for radiofrequency optimized interconnects for a quantum processor are disclosed. In the illustrative embodiment, signals are carried in coplanar waveguides on a surface of a quantum processor die. A ground ring surrounds the signals and is connected to the ground conductors of each coplanar waveguide. Wire bonds connect the ground ring to a ground of a circuit board. The wire bonds provide both an electrical connection from the quantum processor die to the circuit board as well as increased thermal coupling between the quantum processor die and the circuit board, increasing cooling of the quantum processor die.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: Intel CorporationInventors: Hubert C. George, Ravi Pillarisetty, JongSeok Park, Stefano Pellerano, Lester F. Lampert, Thomas F. Watson, Florian Luthi, James S. Clarke
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Publication number: 20230198575Abstract: A wireless communication device can include a channel matching network. The channel matching network includes a pair of coupled lines coupled to the input port, and a capacitive element coupled between the pair of coupled lines and an antenna load.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Ritesh Bhat, Stefano Pellerano, Christopher Hull
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Publication number: 20230198470Abstract: An amplifier, communication device and method of amplification are disclosed. An RF signal is amplified by a Doherty power amplifier (DPA). The DPA has a main amplifier with a Class-AB amplifier in parallel with a Class-C amplifier. When the RF signal power is smaller than 6 dB PBO, the Class-AB amplifier provides the main amplifier amplification; when the RF signal is between 6 dB PBO and 0 dB PBO, both the Class-AB and Class-C amplifiers provide the main amplifier amplification.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Inventors: Stefano Pellerano, Chuanzhao Yu, JongSeok Park, LiChung Tony Chang
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Publication number: 20230196152Abstract: An array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (EDSR) of the qubits. Quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Florian Luethi, Hubert C. George, Felix Frederic Leonhard Borjans, Simon Schaal, Lester Lampert, Thomas Francis Watson, Jeanette M. Roberts, Jong Seok Park, Sushil Subramanian, Stefano Pellerano
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Publication number: 20230186142Abstract: Technologies for high-speed interfaces for cryogenic quantum control are disclosed. In the illustrative embodiment, a die for quantum/classical interface circuitry includes digital circuitry operating in a first clock domain and analog circuitry operating in a second clock domain. Clock domain crossing circuitry facilitates asynchronous data transfer from the digital circuitry to the analog circuitry. The illustrative clock domain crossing circuitry includes a first asynchronous first-in-first-out (FIFO) queue at the border of the first clock domain. The first asynchronous FIFO queue is connected to a second asynchronous FIFO queue at the border of the second clock domain.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Todor Mladenov, JongSeok Park, Stefano Pellerano, Sushil Subramanian
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Publication number: 20230153125Abstract: Technologies for signal conditioning for signals for qubits are disclosed. In the illustrative embodiment, a finite impulse response filter is applied to a control signal for a target qubit to filter out a frequency corresponding to a collateral qubit. An infinite impulse response filter is then applied to the signal after the finite impulse response filter, which amplifies some of the frequencies filtered out by the finite impulse response, narrowing the bandwidth that is filtered out. Such an approach reduces the attenuation of the signal and can be used to reduce memory requirements of quantum/classical interface circuitry.Type: ApplicationFiled: November 16, 2021Publication date: May 18, 2023Applicant: Intel CorporationInventors: Sushil Subramanian, Stefano Pellerano, Todor Mladenov, JongSeok Park
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Publication number: 20230155573Abstract: Technologies for impedance matching networks for qubits are disclosed. In one illustrative embodiment, an impedance matching network matches a 50 Ohm transmission line to a spin qubit with a state-dependent resistance of 100 kiloohms to 105 kiloohms. The illustrative impedance matching network is tunable, allowing the impedance transformation ratio to be changed without significantly changing the matching frequency of the impedance matching network. In some embodiments, the impedance matching network matches a 50 Ohm transmission line to a lower-resistance state of a qubit. In other embodiments, the impedance matching network matches a 50 Ohm transmission line to an impedance value in between a lower-resistance state and a higher-resistance state of a qubit.Type: ApplicationFiled: November 17, 2021Publication date: May 18, 2023Applicant: Intel CorporationInventors: Stefano Pellerano, JongSeok Park, Lester F. Lampert, Sushil Subramanian, Thomas F. Watson
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Publication number: 20230145401Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.Type: ApplicationFiled: December 27, 2022Publication date: May 11, 2023Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
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Publication number: 20230098856Abstract: A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.Type: ApplicationFiled: September 22, 2021Publication date: March 30, 2023Inventors: Somnath Kundu, Stefano Pellerano, Brent R. Carlton
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Publication number: 20220407544Abstract: Radio communication circuits, radio transmitters, and methods are provided in this disclosure. The radio communication circuit may include a modulator configured to provide a first modulated signal including a carrier signal at a carrier frequency, and a second modulated signal including the carrier signal at the carrier frequency. The radio communication circuit may further include a phase shift generator configured to receive a first signal based on the first modulated signal and a second signal based on the second modulated signal. The phase shift generator of the radio communication circuit may further be configured to provide a predefined phase difference between the first signal and the second signal.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Inventors: Woorim SHIN, Ritesh A. BHAT, Chuanzhao YU, Stefano PELLERANO
