Abstract: A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

Abstract: A multi-stage voltage multiplication circuit and methodology are provided which use a multi-stage charge pump boosting circuit (210) and two-stage pass gate circuit (220) having complementary power switches (M6, M9, M7, M10) to efficiently develop an output voltage (VOUT) that is higher than the input supply voltage (VDD). By using a two-stage complementary switch to connect boosted clock signals (P1, P2) from a charge pump (210) to the multiplier output (VOUT), return current from the storage capacitor (COUT) to the pumping capacitor (C1, C2) is blocked, thereby increasing power transfer efficiency, even at high clock frequencies. In addition, a boosted auxiliary voltage is generated by an additional boosting stage (230) and applied to the PMOS wells of the pass gate circuit (220), thereby preventing latch-up and backflow.

Abstract: A multi-stage voltage multiplication circuit and methodology are provided which use a multi-stage charge pump boosting circuit (210) and two-stage pass gate circuit (220) having complementary power switches (M6, M9, M7, M10) to efficiently develop an output voltage (VOUT) that is higher than the input supply voltage (VDD). By using a two-stage complementary switch to connect boosted clock signals (P1, P2) from a charge pump (210) to the multiplier output (VOUT), return current from the storage capacitor (COUT) to the pumping capacitor (C1, C2) is blocked, thereby increasing power transfer efficiency, even at high clock frequencies. In addition, a boosted auxiliary voltage is generated by an additional boosting stage (230) and applied to the PMOS wells of the pass gate circuit (220), thereby preventing latch-up and backflow.

Abstract: A device having a temperature sensor device is disclosed. The temperature sensor device includes a complementary to absolute temperature (CTAT) module and a reference module. Both the temperature sensor and the reference voltage module provide signals, that vary in a complementary relationship with the variation in temperature. While the signals can be voltages or currents, for purposes of discussion the signals are discussed in terms of voltages herein. The reference module provides a signal that has a relatively small variation with temperature as compared to the variation in a signal provided by the CTAT module. The signals are provided to a comparator, which provides a temperature control signal based on a comparison of the input signals.

Abstract: A touch panel detection circuit includes current limiting circuitry that has a first portion coupled between a first supply voltage terminal and a first input node and a second portion coupled between a second input node and a second supply voltage terminal. Programmable precharge circuitry connects the first input node to the first supply voltage terminal via a conductive path that is in parallel with the first portion of the current limiting circuitry and precharges the first input node to a predetermined voltage. Comparison circuitry is coupled to the programmable precharge circuitry and to the first input node. The comparison circuitry detects a change in resistance between the first input node and the second input node and provides a signal in response thereto when the comparison circuitry is enabled by the programmable precharge circuitry.

Abstract: A voltage reference includes a first cell configured to receive a first proportional to absolute temperature (PTAT) current and a second cell configured to receive a second PTAT current. The first cell includes a diode-connected stack of insulated-gate field-effect transistors (IGFETs). The diode-connected stack of IGFETs includes a first transistor that is configured to be biased in a triode weak inversion region. The second cell includes a diode-connected stack of IGFETs and a serially coupled resistor. A magnitude of the second PTAT current is based on a drain-to-source voltage of the first transistor and a value of the serially coupled resistor. The voltage reference provides a reference voltage at a reference node of the second cell based on the second PTAT current.

Abstract: A voltage reference includes a first cell configured to receive a first proportional to absolute temperature (PTAT) current and a second cell configured to receive a second PTAT current. The first cell includes a diode-connected stack of insulated-gate field-effect transistors (IGFETs). The diode-connected stack of IGFETs includes a first transistor that is configured to be biased in a triode weak inversion region. The second cell includes a diode-connected stack of IGFETs and a serially coupled resistor. A magnitude of the second PTAT current is based on a drain-to-source voltage of the first transistor and a value of the serially coupled resistor. The voltage reference provides a reference voltage at a reference node of the second cell based on the second PTAT current.

Abstract: A system and method for decoding a received data stream is disclosed. The method includes detecting first and second data transitions of a received data stream. Each of the data transitions is of a first transition type (e.g. rising or falling transition). The time interval between the data transitions is measured, and a logic value of a data bit encoded in the data stream is decoded based on the measured time interval. By decoding the data stream based on the time intervals between data transitions, the number of decoding errors due to timing changes in the data stream (such as changes due to drift or jitter in the data stream) is reduced.

Abstract: A method and system for decoding a received data stream are disclosed. The appropriate time interval to decode the received data stream is derived from the data stream itself. A header of the data stream is analyzed to determine two sets of time ranges, each set of time ranges corresponding to a set of possible data transmission intervals. A preamble of the header contains timing information for development of a first set of time ranges to decode a synchronization word of the header. The synchronization word contains both data information and timing information to develop the second set of time ranges. The data information included in the header is used validate the data stream for the receiving device. The second set of time ranges is used to decode a data payload portion of the data stream.

Abstract: A device having a temperature sensor device is disclosed. The temperature sensor device includes a complementary to absolute temperature (CTAT) module and a reference module. Both the temperature sensor and the reference voltage module provide signals, that vary in a complementary relationship with the variation in temperature. While the signals can be voltages or currents, for purposes of discussion the signals are discussed in terms of voltages herein. The reference module provides a signal that has a relatively small variation with temperature as compared to the variation in a signal provided by the CTAT module. The signals are provided to a comparator, which provides a temperature control signal based on a comparison of the input signals.

Abstract: A system and method for decoding a received data stream is disclosed. The method includes detecting first and second data transitions of a received data stream. Each of the data transitions is of a first transition type (e.g. rising or falling transition). The time interval between the data transitions is measured, and a logic value of a data bit encoded in the data stream is decoded based on the measured time interval. By decoding the data stream based on the time intervals between data transitions, the number of decoding errors due to timing changes in the data stream (such as changes due to drift or jitter in the data stream) is reduced.