Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.