Patents by Inventor Stefano Tonello
Stefano Tonello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7807480Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.Type: GrantFiled: December 14, 2007Date of Patent: October 5, 2010Assignee: PDF Solutions, Inc.Inventors: Brian Stine, Victor Kitch, Mark Zwald, Stefano Tonello
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Publication number: 20090140762Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.Type: ApplicationFiled: February 10, 2009Publication date: June 4, 2009Applicant: PDF Solutions, Inc.Inventors: Christopher Hess, Angelo Rossoni, Stefano Tonello, Michele Squicciarini, Michele Quarantelli
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Patent number: 7489151Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.Type: GrantFiled: October 3, 2005Date of Patent: February 10, 2009Assignee: PDF Solutions, Inc.Inventors: Christopher Hess, Angelo Rossoni, Stefano Tonello, Michele Squicciarini, Michele Quarantelli
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Patent number: 7487474Abstract: An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.Type: GrantFiled: November 17, 2003Date of Patent: February 3, 2009Assignee: PDF Solutions, Inc.Inventors: Dennis Ciplickas, Joe Davis, Christopher Hess, Sherry Lee, Enrico Malavasi, Abdulmobeen Mohammad, Ratibor Radojcic, Brian Stine, Rakesh Vallishayee, Stefano Zanella, Nicola Dragone, Carlo Guardiani, Michel Quarantelli, Stefano Tonello, Joshi Aniruddha
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Publication number: 20080169466Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.Type: ApplicationFiled: December 14, 2007Publication date: July 17, 2008Applicant: PDF Solutions, Inc.Inventors: Brian Stine, Victor Kitch, Mark Zwald, Stefano Tonello
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Publication number: 20070075718Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.Type: ApplicationFiled: October 3, 2005Publication date: April 5, 2007Applicant: PDF Solutions, Inc.Inventors: Christopher Hess, Angelo Rossoni, Stefano Tonello, Michele Squicciarini, Michele Quarantelli
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Publication number: 20060101355Abstract: An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined.Type: ApplicationFiled: November 17, 2003Publication date: May 11, 2006Applicant: PDF Solutions, Inc.Inventors: Dennis Ciplickas, Joe Davis, Christopher Hess, Sherry Lee, Enrico Malavasi, Abdulmobeen Mohammad, Ratibor Radojcic, Brian Stine, Rakesh Vallishayee, Stefano Zanella, Nicola Dragone, Carlo Guardiani, Michel Quarantelli, Stefano Tonello, Joshi Aniruddha
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Patent number: 6380592Abstract: A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.Type: GrantFiled: November 25, 1998Date of Patent: April 30, 2002Assignee: STMicroelectronics S.r.l.Inventors: Michael Tooher, Stefano Tonello
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Publication number: 20020003244Abstract: A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.Type: ApplicationFiled: November 25, 1998Publication date: January 10, 2002Inventors: MICHAEL TOOHER, STEFANO TONELLO