Abstract: An integrated circuit comprises a circuit module, a first function circuit, and a second function circuit. The first function circuit is configured to he operational in response to a first type logic signal at a first pin and the second function circuit is configured to be operational in response to a second type logic signal at the first pin. The type of logic signal at the first pin is determined by the circuit module. Based on the determined type of logic signal, the circuit module is configured to activate the appropriate function circuit and provide function related signaling for operation at a second pin. The circuit module allows the pins of the integrated circuit to be shared between the first and second function circuits, thus minimizing the number of pins required for multi-functional circuits on the integrated circuit.

Abstract: Systems, methods, and circuits provide a digital frequency synthesizer where the output of the frequency synthesizer is a fractional factor of an input signal frequency. The digital frequency synthesizer may comprise a time to digital converter. A ramp offset signal may be added to the output of the time to digital converter. The ramp offset signal may be added to the output of a TDC until a reference dock signal reaches a value of pi. At such a point, the reference clock signal may be switched and the ramp offset signal may be restarted. As such, a frequency offset may be introduced at the input of the time to digital converter where the frequency offset may be modified by changing the slope of the ramp offset signal.

Abstract: Systems, methods, and circuits provide a digital frequency synthesizer where the output of the frequency synthesizer is a fractional factor of an input signal frequency. The digital frequency synthesizer may comprise a time to digital converter. A ramp offset signal may be added to the output of the time to digital converter. The ramp offset signal may be added to the output of a TDC until a reference dock signal reaches a value of pi. At such a point, the reference clock signal may be switched and the ramp offset signal may be restarted. As such, a frequency offset may be introduced at the input of the time to digital converter where the frequency offset may be modified by changing the slope of the ramp offset signal.

Abstract: Systems, methods, and circuits provide a time to digital converter comprising a sigma-delta modulator. The sigma-delta based time to digital converter may receive an analog signal representing a phase error between a reference clock signal and a feedback clock signal and generate a digital signal representing the phase error. The sigma-delta modulator may comprise a subtractor, an integrator, a feedback path, and a quantizer. The subtractor may receive the analog signal and subtract a feedback signal from the analog signal and the integrator may integrate the output of the subtractor. The sigma-delta modulator may accumulate a voltage or a charge over a capacitor as pulses are received from the analog signal and after a number of clock cycles, the capacitor may be discharged to generate a pulse in an output signal.

Abstract: Transmitter waveform dispersion penalty (“TWDP”) is decreased in a transmitter. A binary data signal is received for transmission over a channel that exhibits TWDP. The data signal is shifted less than a full clock cycle to generate at least one post cursor signal. The post cursor signal is subtracted from the data signal to generate a transmitter output data signal for transmission over the channel. In addition to decreasing TWDP, data dependent jitter is also reduced for data transmission across a channel that exhibits a multi-pole transmission characteristic. A main data signal and at least one cursor signal, which is shifted at least a portion of a clock period from the main data signal, is generated. The cursor signal is filtered to filter out effects based on the second pole of the multi-pole transmission characteristic. The main data signal is subtracted from the filtered cursor signal to generate the transmitter output data signal.

Abstract: Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.

Abstract: A method and system to drive large off-chip loads, such as, for example, laser diodes, wherein the system includes an integrated circuit coupled to an external differential diode load. Alternatively, the external diode load may be driven single-ended. The integrated circuit includes a data buffer device and a clock buffer device. The integrated circuit also includes a multiplexer device coupled to the clock buffer device configured to multiplex a data input signal and a clock input signal received at respective inputs of the integrated circuit. If the external diode is single-ended, the data input signal is transmitted to the data buffer device, which is then used solely to drive the diode load. If the diode load is differential, the data buffer device receives the data input signal. At the same time, the multiplexer device receives both the data input signal and the clock input signal and selects the data signal to drive the clock buffer device.

Abstract: An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.

Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.

Abstract: A clock and data recovery circuit may comprise a first transmission line comprising a plurality of segments of a first predetermined length. The first transmission line receives and propagates a clock signal through the segments of the first predetermined length. The clock and data recovery circuit may further comprise a second transmission line comprising a plurality of segments of a second predetermined length. The second transmission line receives data from a serial bit stream and propagates the data through the segments of the second predetermined length. In some embodiments, the first or second transmission line further comprise taps to extract, from the segments of the second predetermined length, a plurality of delayed data signals. The clock and data recovery circuit may further comprise a plurality of sampling circuits, coupled to the first and second transmission lines, to generate samples from the delayed data signals and the delayed clock signals.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed.

Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed.

Abstract: A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.

Abstract: Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.

Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.