Patents by Inventor Steffany Ann Lacierda Moreno

Steffany Ann Lacierda Moreno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022841
    Abstract: A semiconductor device assembly includes a package substrate having a top side including a plurality of bondable features, at least one integrated circuit (IC) die including a substrate having at least a semiconductor surface including circuitry configured for realizing at least one function including nodes coupled to bond pads with metal posts on the bond pads. The metal posts are attached by a solder joint to the bondable features. The solder joint has a void density of less than or equal to (?) 5% of a cross-sectional area of the solder joint.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Inventors: James Raymond Maliclic Baello, Steffany Ann Lacierda Moreno, Jose Carlos Arroyo
  • Patent number: 12132027
    Abstract: A semiconductor device assembly includes a package substrate having a top side including a plurality of bondable features, at least one integrated circuit (IC) die including a substrate having at least a semiconductor surface including circuitry configured for realizing at least one function including nodes coupled to bond pads with metal posts on the bond pads. The metal posts are attached by a solder joint to the bondable features. The solder joint has a void density of less than or equal to (?) 5% of a cross-sectional area of the solder joint.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: October 29, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Raymond Maliclic Baello, Steffany Ann Lacierda Moreno, Jose Carlos Arroyo
  • Patent number: 11929308
    Abstract: In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steffany Ann Lacierda Moreno, John Carlo Cruz Molina, Rafael Jose Lizares Guevara
  • Publication number: 20230260958
    Abstract: In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Rafael Jose Lizares Guevara, John Carlo Cruz Molina, Steffany Ann Lacierda Moreno
  • Publication number: 20230187223
    Abstract: A semiconductor package includes a leadframe forming a plurality of leads with a die attach site, a semiconductor die including a set of die contacts mounted to the die attach site in a flip chip configuration with each die contact of the set of die contacts electrically connected to leadframe via one of a set of solder joints, a set of solder joint capsules covering each of the set of solder joints against the leadframe, a clip mounted to the leadframe over the semiconductor die with a clip solder joint. The solder joint capsules restrict flow of the solder joints of the semiconductor die contacts in the flip chip configuration such that the solder remains in place if remelted during later clip solder reflow.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 15, 2023
    Inventors: James Raymond Maliclic Baello, Steffany Ann Lacierda Moreno
  • Publication number: 20230137852
    Abstract: In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Steffany Ann Lacierda Moreno, John Carlo Cruz Molina, Rafael Jose Lizares Guevara
  • Patent number: 11637083
    Abstract: In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 25, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rafael Jose Lizares Guevara, John Carlo Cruz Molina, Steffany Ann Lacierda Moreno
  • Patent number: 11600498
    Abstract: A semiconductor package includes a leadframe forming a plurality of leads with a die attach site, a semiconductor die including a set of die contacts mounted to the die attach site in a flip chip configuration with each die contact of the set of die contacts electrically connected to leadframe via one of a set of solder joints, a set of solder joint capsules covering each of the set of solder joints against the leadframe, a clip mounted to the leadframe over the semiconductor die with a clip solder joint. The solder joint capsules restrict flow of the solder joints of the semiconductor die contacts in the flip chip configuration such that the solder remains in place if remelted during later clip solder reflow.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Raymond Maliclic Baello, Steffany Ann Lacierda Moreno
  • Publication number: 20220320038
    Abstract: In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Rafael Jose Lizares Guevara, Juan Carlo Cruz Molina, Steffany Ann Lacierda Moreno
  • Publication number: 20220122940
    Abstract: A semiconductor device assembly includes a package substrate having a top side including a plurality of bondable features, at least one integrated circuit (IC) die including a substrate having at least a semiconductor surface including circuitry configured for realizing at least one function including nodes coupled to bond pads with metal posts on the bond pads. The metal posts are attached by a solder joint to the bondable features. The solder joint has a void density of less than or equal to (?) 5% of a cross-sectional area of the solder joint.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 21, 2022
    Inventors: James Raymond Maliclic Baello, Steffany Ann Lacierda Moreno, Jose Carlos Arroyo
  • Publication number: 20210202269
    Abstract: A semiconductor package includes a leadframe forming a plurality of leads with a die attach site, a semiconductor die including a set of die contacts mounted to the die attach site in a flip chip configuration with each die contact of the set of die contacts electrically connected to leadframe via one of a set of solder joints, a set of solder joint capsules covering each of the set of solder joints against the leadframe, a clip mounted to the leadframe over the semiconductor die with a clip solder joint. The solder joint capsules restrict flow of the solder joints of the semiconductor die contacts in the flip chip configuration such that the solder remains in place if remelted during later clip solder reflow.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: James Raymond Maliclic Baello, Steffany Ann Lacierda Moreno
  • Publication number: 20210066239
    Abstract: An example apparatus includes a semiconductor die including a bond pad; a conductive post on the bond pad; a solder joint electrically connecting the conductive post to a substrate; and ink residue of solder mask material surrounding a portion of the solder joint, the ink residue covering a portion of the substrate. Methods for forming the apparatus are disclosed.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 4, 2021
    Inventor: Steffany Ann Lacierda Moreno