Patents by Inventor Steffen Breuer

Steffen Breuer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150162186
    Abstract: The invention relates to a method for producing a layer by means of MOVPE, wherein the layer comprises or consists of at least one III-V compound semiconductor and carbon, wherein the compound semiconductor comprises at least one element of main group III of the periodic table which is selected from any of gallium, aluminum, indium and/or boron, and wherein the compound semiconductor comprises at least nitrogen and wherein the compound semiconductor comprises optionally at least one further element of main group V which is selected from any of phosphorus and/or arsenic, wherein the method comprises the steps of: introducing a substrate into a vacuum chamber; evacuating the vacuum chamber to a background pressure; heating the substrate to a predefinable temperature; introducing at least one precursor gas into the vacuum chamber, said gas comprising or consisting of nitrogen; introducing at least one precursor comprising an organometallic compound into the vacuum chamber; introducing at least one hydrocarbon co
    Type: Application
    Filed: December 10, 2014
    Publication date: June 11, 2015
    Inventors: Klaus Köhler, Stefan Müller, Steffen Breuer
  • Patent number: 7084043
    Abstract: A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: August 1, 2006
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Steffen Breuer, Matthias Goldbach, Joern Luetzen, Dirk Schumann
  • Publication number: 20040197965
    Abstract: A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.
    Type: Application
    Filed: March 5, 2004
    Publication date: October 7, 2004
    Inventors: Albert Birner, Steffen Breuer, Matthias Goldbach, Joern Luetzen, Dirk Schumann