Abstract: Methods, systems, and devices for self-refresh exit detection for memory devices are described. The described techniques provide for a memory system to indicate whether the memory system is in a self-refresh mode or not. The memory system may initiate a self-refresh operation for one or more memory cells of the memory system. The memory system may set a mode register to a first value based on initiating the self-refresh operation. The first value of the mode register may indicate that the self-refresh operation is being executed. The memory system may determine whether to reset the mode register to a second value based on a status of the self-refresh operation. The second value of the mode register may indicate that the self-refresh operation is complete. A host system may poll the mode register to determine the status of the self-refresh operation at the memory system.

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

Abstract: Implementations described herein relate to emergency data storing operation selection. In some implementations, a memory device may be configured to receive a peripheral component interconnect power loss notification (PLN) signal and a peripheral component interconnect express reset (PERST) signal. The memory device may be configured to determine whether to initiate a first data storing operation or a second data storing operation based on the PERST signal state based on a falling edge of the PLN signal. The memory device may be configured to selectively initiate the first data storing operation or the second data storing operation. The first data storing operation may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing operation may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss.

Abstract: In some implementations, a memory system may configure an association of queue resources to identifiers of respective virtual machines of one or more virtual machines, wherein the queue resources are associated with multiple queues of a universal flash storage (UFS) host. The memory system may receive a request indicating an identifier and one or more queue resources. The memory system may perform an action, via a UFS device, associated with the request based on the identifier, the one or more queue resources, and the association.

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Abstract: Implementations described herein relate to a two-stage emergency data storing operation. In some implementations, a memory device may detect a power loss notification signal that indicates a power loss condition of the memory device. The memory device may read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage. The first data storing stage may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss. The memory device may initiate the data storing operation and may selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage.

Abstract: Methods, systems, and devices for safety and security for memory are described. In some examples, data associated with a memory device may be authenticated before an associated operation is executed. The data may be authenticated before it is executed at a volatile memory. The data may be associated with a hash (e.g., a first hash) and may be communicated from the memory device to a host device. At the host device, the data and the first hash may be written (e.g., stored) to temporary storage, such as a cache. Once stored to the cache, the host device may generate an additional hash (e.g., a second hash) related to the data using a key inaccessible to the memory device. If the first hash and second hash match, the data may be authenticated and one or more operations may be executed.

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Abstract: Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.

Abstract: Data associated with a memory device may be authenticated before an associated operation is executed. The data may be authenticated before it is executed at a volatile memory. The data may be associated with a hash (e.g., a first hash) and may be communicated from the memory device to a host device. At the host device, the data and the first hash may be written (e.g., stored) to temporary storage, such as a cache. Once stored to the cache, the host device may generate an additional hash (e.g., a second hash) related to the data using a key inaccessible to the memory device. If the first hash and second hash match, the data may be authenticated and one or more operations may be executed.

Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.

Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.

Abstract: Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

Abstract: In some implementations, a memory device may receive, from a host device, a hardware reset signal. The memory device may determine that a level associated with the hardware reset signal satisfies a threshold for a period of time. The memory device may determine, based on the hardware reset signal satisfying the threshold for the period of time, that the host device is expected to power down the memory device. The memory device may complete an ongoing memory operation within a remaining time period based on the determination that the host device is expected to power down the memory device.

Abstract: Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Abstract: Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.