Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with a data inversion and unidirectional error detection are described. An apparatus for data inversion and unidirectional error detection can include a memory device and a processing device communicatively coupled to the memory device. The processing device can be configured to encode a plurality of binary data bits in an information word, encode the information word using a unidirectional error detecting code, write the encoded information word to the memory device, read the encoded information word from the memory device, and detect an error in the information word using a unidirectional error detecting code. The encoding can include inverting the plurality of binary data bits and adding an inversion data bit to the information word.

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with a data inversion and unidirectional error detection are described. An apparatus for data inversion and unidirectional error detection can include a memory device and a processing device communicatively coupled to the memory device. The processing device can be configured to encode a plurality of binary data bits in an information word, encode the information word using a unidirectional error detecting code, write the encoded information word to the memory device, read the encoded information word from the memory device, and detect an error in the information word using a unidirectional error detecting code. The encoding can include inverting the plurality of binary data bits and adding an inversion data bit to the information word.

Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.

Abstract: Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

Abstract: Methods, systems, and devices for security techniques for low power state of memory device are described. A host device may initiate a low power state of a memory device. The host device may store a first value of a counter associated with the memory device operating in the low power state and transmit a command to the memory device to enter the low power state. The memory device may increment the counter based on receiving the command and increment the counter to a second value. The host device may validate the memory device based on a difference between the first value of the counter stored by the host device and the second value of the counter.

Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.

Abstract: Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.

Abstract: Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.

Abstract: Methods, systems, and devices for error type indication are described. A memory device may detect an error while performing an error detection procedure for a codeword. The memory device may transmit to a host device one or more bits, which may be one or more error flags, that indicate the type of error detected by the memory device. By transmitting the one or more bits to a requesting device, for example a host device, the memory device may indicate the detected presence of a particular type of error in the set of data that is returned to the requesting device.

Abstract: Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.

Abstract: Methods, systems, and devices for safety and security for memory are described. In some examples, data associated with a memory device may be authenticated before an associated operation is executed. The data may be authenticated before it is executed at a volatile memory. The data may be associated with a hash (e.g., a first hash) and may be communicated from the memory device to a host device. At the host device, the data and the first hash may be written (e.g., stored) to temporary storage, such as a cache. Once stored to the cache, the host device may generate an additional hash (e.g., a second hash) related to the data using a key inaccessible to the memory device. If the first hash and second hash match, the data may be authenticated and one or more operations may be executed.

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

Abstract: Methods, systems, and devices for security techniques for low power state of memory device are described. A host device may initiate a low power state of a memory device. The host device may store a first value of a counter associated with the memory device operating in the low power state and transmit a command to the memory device to enter the low power state. The memory device may increment the counter based on receiving the command and increment the counter to a second value. The host device may validate the memory device based on a difference between the first value of the counter stored by the host device and the second value of the counter.

Abstract: A method and device for transmitting audio data and text data to an RDS capable radio receiver by a wireless device is disclosed. The device includes a receiver for scanning a frequency range to detect an available radio frequency based on predetermined criteria. The device also includes a transmitter for transmitting data on a detected frequency that comprises RDS message data. Other systems and methods are also disclosed.

Abstract: A method and device for transmitting audio data and text data to an RDS capable radio receiver by a wireless device is disclosed. The device includes a receiver for scanning a frequency range to detect an available radio frequency based on predetermined criteria. The device also includes a transmitter for transmitting data on a detected frequency that comprises RDS message data. Other systems and methods are also disclosed.

Abstract: A method and a circuit for the digital correction of a frequency of a signal, especially for use in a transmitter/receiver circuit include rotating a signal “pointer” (i0, q0) using a CORDIC algorithm, through a predetermined angle in a complex I/Q plane corresponding to a correction frequency. The CORDIC algorithm includes micro-rotation blocks corresponding to N stages, and a character table and a register.

Abstract: A digital comb filter contains filter stages. Each filter stage has a latch disposed at a filter stage input, which latch, by outputting each input data value twice in each case doubles the sampling rate. Each filter stage further has a filter structure, a partial transfer function {overscore (H)} (z) of which is {overscore (H)}(z)?(1+z?1)k?1, where k is an order of the filter device and z?1 is the z transform of a delay by one sampling pulse. The implementation according to the invention does not require an error correction circuit.

Abstract: A digital comb filter contains filter stages. Each filter stage has a latch disposed at a filter stage input, which latch, by outputting each input data value twice in each case doubles the sampling rate. Each filter stage further has a filter structure, a partial transfer function {overscore (H)}(z) of which is {overscore (H)}(z)&agr;(1+z−1)k−1, where k is an order of the filter device and z−1 is the z transform of a delay by one sampling pulse. The implementation according to the invention does not require an error correction circuit.