Patents by Inventor Steffen Dolling

Steffen Dolling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230258720
    Abstract: A system-on-chip integrated circuit device includes a plurality of functional circuit modules, at least a first circuit module of the plurality of functional circuit modules operating under a first protocol, the first protocol being an interface protocol for communicating outside the system-on-chip integrated circuit device, an interconnect fabric coupled to the functional circuit modules in the plurality of functional circuit modules, and a built-in self-test circuit module coupled to the interconnect fabric. The built-in self-test circuit is configured to test one or more selected functional circuit modules in the plurality of functional circuit modules, including at least the first circuit module under the first protocol for communicating outside the system-on-chip integrated circuit device, by routing test data through the one or more selected functional circuit modules.
    Type: Application
    Filed: February 16, 2023
    Publication date: August 17, 2023
    Inventors: Xiongzhi Ning, Yuyi Tang, Steffen Dolling
  • Publication number: 20220271853
    Abstract: A network includes a first plurality of nodes operating in a first clock domain based on a first clock source, a second plurality of nodes operating in a second clock domain based on a second clock source, and synchronization circuitry accessible to both of the clock domains without requiring network traffic between the clock domains. The synchronization circuitry is configured to periodically calculate a drift rate between the time of day in the respective clock domains. Each node in one of the clock domains is configured to, when sending a message to a node in the other of the clock domains, calculate a time of day in the other of the clock domains based on an actual time of day in the one of the clock domains and the drift rate, and to include, in the message to the node in the other clock domain, the calculated time of day.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 25, 2022
    Inventors: Olaf Mater, Lukas Reinbold, Xiongzhi Ning, Steffen Dolling
  • Patent number: 9804824
    Abstract: A system including a bus, a buffer, a bridge and a module. The bus is connected to multiple devices. The buffer is connected to the bus. The buffer is configured to transfer data to or receive the data from one or more of the devices, forward the data during a forwarding mode, and receive the data during a gathering mode. The module is configured to determine whether a first condition and/or a second condition exist. Based on whether the first condition exists, the module is configures the bridge to transfer the data from the buffer to a host system or transitions the buffer from the gathering mode to the forwarding mode to forward the data from the buffer to the one or more of the devices. Based on whether the second condition exists, the module is configured to transition the buffer from the forwarding mode to the gathering mode.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: October 31, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xiongzhi Ning, Steffen Dolling
  • Patent number: 9128920
    Abstract: A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 8, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Xiongzhi Ning, Steffen Dolling, Markus Althoff