Abstract: A modification of a predetermined, memory-size-dependant number of nonvolatile memory cells turns them into ROM cells with a fixed content pattern. Since these additional ROM cells do not require much effort during manufacturing and use only small additional space on the memory chip or the integrated circuit, but provide significant advantage for testing. When using pairs of essentially symmetrical non-volatile memory cells, each pair having a common bit line, the removal or interruption of this bitline contact may serve to impress a fixed value, e.g. a ‘0’, into this pair and vice versa. During test, a simple and therefore only minimal time requiring pattern, preferably a checkerboard pattern, is written into and read from the non-volatile memory, allowing a quick determination of the decoders' correct function.

Abstract: This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. To reduce power consumption, the processor clock rates are often varied depending on the current performance requirements. Differing clock rates of processors sharing a non-volatile memory leads to relatively long read access times of the latter, since the particular microprocessor fetching the data from the memory is usually halted until the data are available. When dual or multi-port non-volatile memory and multiple asynchronous clocks are used, access times are even longer since clock synchronization between the ports is necessary. The present invention overcomes this problem by providing a plurality of wait timers, preferably one dedicated to each processor, advantageously each being clocked synchronously with its associated processor.

Abstract: The invention relates to an arrangement for testing integrated circuits, to a test system (2), to a circuit (1) to be tested, and to a method of testing logic circuits, where the test system (2) includes a programmable algorithmic test vector generator (4) which generates test vectors in real time so as to transfer these vectors to the circuit (1) to be tested.

Abstract: Testing an integrated circuit IC (2) with an embedded or integrated non-volatile memory (3), in particular an embedded memory, an EPROM or EEPROM, is particularly difficult because mass production and low prices and minimal profit margins require that the testing, which usually requires expensive and large equipment, can be done in a minimum of time. Usually, the testing of an embedded memory (3) is a kind of bottleneck during manufacturing. A test structure and design and an associated test method this test time for an embedded memory. In essence, a few test devices (8,9) integrated into the IC (2), use of the serial port provided on the IC, and an appropriate test design of a built-in self test whereby predetermined regular test patterns are written automatically into the embedded memory and an automated memory readout is compressed on the IC for a serial readout from it, allow a fast test of the embedded memory and thus circumvent the aforementioned bottleneck.

Abstract: This invention relates to the structure and design of a non-volatile memory, in particular to such memories embedded or integrated into integrated circuits (ICs). To solve the problem of excessive test times for such memories, especially the testing of the associated decoders, a modification of a predetermined, memory-size-dependant number of nonvolatile memory cells turns them into ROM cells with a fixed content pattern. Since these additional ROM cells are just modified non-volatile cells, they differ only slightly from the latter. Thus, they do not require much effort during manufacturing and, even more important, use only small additional space on the memory chip or the integrated circuit, but provide significant advantage for the testing. When using pairs of essentially symmetrical non-volatile memory cells, each pair having a common bit line, the removal or interruption of this bitline contact may serve to impress a fixed value, e.g. a ‘0’, into this pair and vice versa.

Abstract: Testing an integrated circuit IC (2) with an embedded or integrated non-volatile memory (3), in particular an embedded memory, an EPROM or EEPROM, is particularly difficult because mass production and low prices and minimal profit margins require that the testing, which usually requires expensive and large equipment, can be done in a minimum of time. Usually, the testing of an embedded memory (3) is a kind of bottleneck during manufacturing. The present invention describes a test structure and design and an associated test method which minimize this test time for an embedded memory.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion.

Abstract: Circuit configuration for signal transmission from a finite state machine that can be operated at a first clock rate to a finite state machine that can be operated at a second clock rate, the signal from the transmitting finite state machine being transferable through an asynchronous storage element and a synchronous storage element connected thereto, to the receiving finite state machine which is designed for transmitting a reset signal to the asynchronous storage element after the signal transmission.

Abstract: A system (70) comprising a microprocessor (74), a data bus (75) for writing data into a Flash memory device (71) and a data bus (75) for reading data from the Flash memory device (71). The Flash memory device (71) comprises an error correction encoder (72), a Flash memory (71), an error correction decoder (73), and a Flash data bus (75) for interconnecting the error correction encoder (72), the Flash memory (71), and the error correction decoder (73). The data, when being processed by the error correction encoder (72) are converted into a word that comprises a status word (51), a data word (52), and a redundancy word (53). This approach enables error correction with single-bit alterability.

Abstract: This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. To reduce power consumption, the processor clock rates are often varied depending on the current performance requirements. Differing clock rates of processors sharing a non-volatile memory leads to relatively long read access times of the latter, since the particular microprocessor fetching the data from the memory is usually halted until the data are available. When dual or multi-port non-volatile memory and multiple asynchronous clocks are used, access times are even longer since clock synchronization between the ports is necessary. The present invention overcomes this problem by providing a plurality of wait timers, preferably one dedicated to each processor, advantageously each being clocked synchronously with its associated processor.

Abstract: The invention relates to an arrangement for testing integrated circuits, to a test system (2), to a circuit (1) to be tested, and to a method of testing logic circuits, where the test system (2) includes a programmable algorithmic test vector generator (4) which generates test vectors in real time so as to transfer these vectors to the circuit (1) to be tested.

Abstract: This invention relates to the structure and design of integrated circuits (ICs), in particular to the embedding or integration of a non-volatile, so-called flash memory into ICs. To solve the issues created by speed differences of the embedded flash memory compared to the other components on an IC, in particular the microprocessor and/or other memory on the IC, a specific writing interface is provided for the flash memory which makes the latter appear like standard memory from a software viewpoint. This writing interface includes a bank of registers (2) between flash memory (7) and microprocessor (6), essentially being operated by a write controller (1) and a flash bus arbiter (8) and acting, in principle, as a intermediate buffering mechanism controlled by a state machine.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion.