Patents by Inventor Steffen K. Kaldor
Steffen K. Kaldor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7494915Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: GrantFiled: August 9, 2006Date of Patent: February 24, 2009Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Erdem Kaltalioglu, Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Jochen Schacht, Andrew H. Simon, Terry A. Spooner, Yun-Yu Wang, Clement H. Wann, Chih-Chao Yang
-
Patent number: 7378338Abstract: In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.Type: GrantFiled: July 31, 2006Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Steffen K. Kaldor, Hyungjun Kim, Stephen M. Rossnagel
-
Patent number: 7241681Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: GrantFiled: January 12, 2006Date of Patent: July 10, 2007Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
-
Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Patent number: 7241696Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.Type: GrantFiled: December 11, 2002Date of Patent: July 10, 2007Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Jr., Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang -
Patent number: 7214548Abstract: A method, apparatus, and computer program product for flattening a warped substrate. The substrate is placed on a planar surface of a clamping apparatus in direct mechanical contact with the planar surface. The substrate comprises surface regions S1, S2, . . . , SN having an average warpage of W1, W2, . . . , WN, respectively, wherein W1?W2? . . . ?WN and W1?WN. Zones Z1, Z2, . . . , ZN of the planar surface respectively comprise vacuum port groups G1, G2, . . . , GN. Each group comprises at least one vacuum port. N is at least 2. A vacuum pressure PV1, PV2, . . . , PVN is generated at each vacuum port within group G1, G2, . . . , GN, at a time of T1, T2, . . . , TN to clamp surface region S1, S2, . . . , SN to zone Z1, Z2, . . . , ZN, respectively. The vacuum pressure PV1, PV2, . . . , PVN is maintained at the vacuum ports of group G1, G2, . . . , GN, respectively, until time TN+1. T1<T2< . . . <TN<TN+1.Type: GrantFiled: August 30, 2004Date of Patent: May 8, 2007Assignee: International Business Machines CorporationInventors: Mohammed F. Fayaz, Steffen K. Kaldor, Conal E. Murray, Ismail C. Noyan, Anne L. Petrosky
-
Patent number: 7122462Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: GrantFiled: November 21, 2003Date of Patent: October 17, 2006Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Erdem Kaltalioglu, Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Jochen Schacht, Andrew H. Simon, Terry A. Spooner, Yun-Yu Wang, Clement H. Wann, Chih-Chao Yang
-
Patent number: 7098537Abstract: In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.Type: GrantFiled: November 21, 2003Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Steffen K. Kaldor, Hyungjun Kim, Stephen M. Rossnagel
-
Patent number: 7064064Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: GrantFiled: February 16, 2005Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P. E. Smith, Wei-tsu Tseng
-
Patent number: 7052621Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: GrantFiled: June 13, 2003Date of Patent: May 30, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
-
Patent number: 7001835Abstract: A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 ?Ohm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.Type: GrantFiled: November 21, 2003Date of Patent: February 21, 2006Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik A. Kumar, Stephen M. Rossnagel, Andrew H. Simon, Douglas C. La Tulipe, Jr.
-
Patent number: 6975032Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: GrantFiled: December 16, 2002Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P. E. Smith, Wei-tsu Tseng
-
Publication number: 20040251234Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: ApplicationFiled: June 13, 2003Publication date: December 16, 2004Inventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
-
Publication number: 20040113279Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: ApplicationFiled: December 16, 2002Publication date: June 17, 2004Applicant: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P.E. Smith, Wei-tsu Tseng