Abstract: A network on chip comprising: a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant; each quadrant comprising a first cluster and a second cluster; and wherein the first cluster of the first quadrant is directly connected to four clusters comprising: the second cluster of the first quadrant, the second cluster of the second quadrant, the first cluster of the fourth quadrant, and the second cluster of the fourth quadrant. The network on chip architecture optimizes connectivity, fault tolerance, and data transmission efficiency by ensuring each cluster is directly connected to four other clusters. This reduces latency, enhances scalability, and improves load balancing. The modular design simplifies integration and expansion, making it suitable for high-performance, reliable, and efficient multi-core systems. This architecture balances wiring complexity, latency, and power consumption, offering significant advantages over traditional topologies.

Abstract: The invention relates to a snoop filter device, a node controller, a multicomponent computer system, a computer-implemented method, a data processing system and a computer-readable storage medium aiming at enabling improved tracking of a scalable number of cache elements in multiprocessor systems. The invention involves scaling of a snoop filter device according to the number of cache elements that it is desirable to track.

Abstract: The invention relates to a snoop filter device, a node controller, a multicomponent computer system, a computer-implemented method, a data processing system and a computer-readable storage medium aiming at enabling improved tracking of a scalable number of cache elements in multiprocessor systems. The invention involves scaling of a snoop filter device according to the number of cache elements that it is desireable to track.

Abstract: The invention relates to a device for use in maintaining cache coherence in a multiprocessor computing system. The snoop filter device is connectable with a plurality of cache elements, where each cache element comprises a number of cache agents. The snoop filter device comprises a plurality of snoop filter storage locations, where each snoop filter storage location is mapped to one cache element.

Abstract: The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

Abstract: A cache coherent node controller at least includes one or more network interface controllers, each network interface controller includes at least one network interface, and at least two coherent interfaces each configured for communication with a microprocessor. A computer system includes one or more of nodes wherein each node is connected to at least one network switch, each node at least includes a cache coherent node controller.

Abstract: The invention relates to a device for use in maintaining cache coherence in a multiprocessor computing system. The snoop filter device is connectable with a plurality of cache elements, where each cache element comprises a number of cache agents. The snoop filter device comprises a plurality of snoop filter storage locations, where each snoop filter storage location is mapped to one cache element.

Abstract: A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: A cache coherent node controller at least includes one or more network interface controllers, each network interface controller includes at least one network interface, and at least two coherent interfaces each configured for communication with a microprocessor. A computer system includes one or more of nodes wherein each node is connected to at least one network switch, each node at least includes a cache coherent node controller.

Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: Presented herein are systems and methods for checking the integrity of data transmissions between or within one or more digital processing systems by identifying a data characteristic that is likely to change if there is an error in transmission. According to one embodiment, data messages are modified to achieve a selected characteristic according to a predetermined protocol, and changes to the data are recorded in a longitudinal check code (LCC) word, which is used by the receiver to decode the data message and restore the original data.

Abstract: Presented herein are systems and methods for checking the integrity of data transmissions between or within one or more digital processing systems by identifying a data characteristic that is likely to change if there is an error in transmission. According to one embodiment, data messages are modified to achieve a selected characteristic according to a predetermined protocol, and changes to the data are recorded in a longitudinal check code (LCC) word, which is used by the receiver to decode the data message and restore the original data.

Abstract: Presented herein are systems, methods, and devices for transmitting data comprising by comparing a new message with a buffered message representative of a previous message, recording an integer number of differences between the new message and the buffered message, generating a diff-word representative of the integer number of differences between the new message and the buffered message, appending the diff-word to the new message, and sending the new message with the diff-word to a receiver. The diff-word is used by the receiver to determine whether a received new message has the expected number of differences, and to determine whether to accept the new message.

Abstract: Presented herein are systems and methods for checking the integrity of data transmissions between or within one or more digital processing systems by identifying a data characteristic that is likely to change if there is an error in transmission. According to one embodiment, data messages are modified to achieve a selected characteristic according to a predetermined protocol, and changes to the data are recorded in a longitudinal check code (LCC) word, which is used by the receiver to decode the data message and restore the original data.

Abstract: Presented herein are systems, methods, and devices for transmitting data comprising by comparing a new message with a buffered message representative of a previous message, recording an integer number of differences between the new message and the buffered message, generating a diff-word representative of the integer number of differences between the new message and the buffered message, appending the diff-word to the new message, and sending the new message with the diff-word to a receiver. The diff-word is used by the receiver to determine whether a received new message has the expected number of differences, and to determine whether to accept the new message.

Abstract: Presented herein are systems and methods for checking the integrity of data transmissions between or within one or more digital processing systems by identifying a data characteristic that is likely to change if there is an error in transmission. According to one embodiment, data messages are modified to achieve a selected characteristic according to a predetermined protocol, and changes to the data are recorded in a longitudinal check code (LCC) word, which is used by the receiver to decode the data message and restore the original data.