Patents by Inventor Steffen Thiele
Steffen Thiele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230017307Abstract: A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Inventors: Carmelo Giunta, Marcus Nuebling, Steffen Thiele
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Patent number: 11549998Abstract: A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.Type: GrantFiled: July 16, 2021Date of Patent: January 10, 2023Assignee: Infineon Technologies AGInventors: Carmelo Giunta, Marcus Nuebling, Steffen Thiele
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Patent number: 10950509Abstract: A semiconductor device includes a first chip pad, a power semiconductor chip arranged on the first chip pad and including at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.Type: GrantFiled: April 30, 2019Date of Patent: March 16, 2021Assignee: Infineon Technologies AGInventors: Rainald Sander, Thomas Bemmerl, Steffen Thiele
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Publication number: 20190348333Abstract: A semiconductor device comprises a first chip pad, a power semiconductor chip arranged on the first chip pad and comprising at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.Type: ApplicationFiled: April 30, 2019Publication date: November 14, 2019Inventors: Rainald Sander, Thomas Bemmerl, Steffen Thiele
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Patent number: 10451669Abstract: Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.Type: GrantFiled: September 29, 2017Date of Patent: October 22, 2019Assignee: Infineon Technologies AGInventors: Carlos Joao Marques Martins, Aron Theil, Steffen Thiele
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Publication number: 20190101585Abstract: Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Carlos Joao Marques Martins, Aron Theil, Steffen Thiele
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Patent number: 10128750Abstract: A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.Type: GrantFiled: March 4, 2016Date of Patent: November 13, 2018Assignee: Infineon Technologies AGInventors: Andreas Meiser, Steffen Thiele
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Patent number: 9960156Abstract: An integrated semiconductor device is provided. According to an embodiment, the integrated semiconductor device includes a semiconductor body having a first surface with a normal direction defining a vertical direction, an opposite surface, a first area including a vertical power field-effect transistor structure, a second area including a three-terminal step-down level-shifter, and a third area including a three-terminal step-up level-shifter. A terminal of the vertical power field-effect transistor structure is electrically connected with one of the three-terminal step-down level-shifter and the three-terminal step-up level-shifter.Type: GrantFiled: July 9, 2015Date of Patent: May 1, 2018Assignee: Infineon Technologies AGInventors: Franz Hirler, Andreas Meiser, Steffen Thiele
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Patent number: 9829225Abstract: The invention relates to a module for a heat pump, comprising an adsorption-desorption region, wherein in the region a bundle of pipes through which fluid can flow is arranged and a housing encloses the pipe bundle and a movable working medium in a sealing manner, wherein a supporting structure forms a mechanical support of a wall of the housing against the action of an external pressure.Type: GrantFiled: July 19, 2012Date of Patent: November 28, 2017Assignees: MAHLE Behr GmbH & Co. KG, MAHLE International GmbHInventors: Thomas Schiehlen, Steffen Thiele, Thomas Wolff, Eberhard Zwittig, Hans-Heinrich Angermann, Roland Burk, Holger Schroth, Stefan Felber, Steffen Brunner
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Publication number: 20170257025Abstract: A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.Type: ApplicationFiled: March 4, 2016Publication date: September 7, 2017Inventors: Andreas Meiser, Steffen Thiele
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Patent number: 9728580Abstract: A power transistor has a semiconductor body with a bottom side and top side spaced distant from the bottom side in a vertical direction. The semiconductor body includes a plurality of transistor cells, a source zone of a first conduction type, a body zone of a second conduction type, a drift zone of the first conduction type, a drain zone, and a temperature sensor diode having a pn-junction between an n-doped cathode zone and a p-doped anode zone. The power transistor also has a drain contact terminal on the top side, a source contact terminal on the bottom side, a gate contact terminal, and a temperature sense contact terminal on the top side. Depending on the first and second conduction types the anode or cathode zone is electrically connected to the source contact terminal and the other diode zone is electrically connected to the temperature sense contact terminal.Type: GrantFiled: May 13, 2013Date of Patent: August 8, 2017Assignee: Infineon Technologies AGInventors: Andreas Meiser, Steffen Thiele
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Patent number: 9488674Abstract: A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.Type: GrantFiled: July 9, 2014Date of Patent: November 8, 2016Assignee: INFINEON TECHNOLOGIES AGInventors: Carlos Marques Martins, Steffen Thiele, Aron Theil
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Patent number: 9372212Abstract: A circuit is provided, including a first resistor, a second resistor which may have an adjustable resistance, and a control unit. The control unit may be configured to adjust the second resistor to have a first resistance at which a voltage due to a first current flowing through the first resistor is equal to a voltage due to a second current flowing through the second resistor. The control unit may be further configured to adjust the second resistor to have a second resistance at which a voltage due to another first current different from the first current and flowing through the first resistor is equal to the voltage due to the second current flowing through the second resistor. The control unit may be further configured to adjust the second resistor to have a third resistance based on at least a difference of the first resistance and the second resistance.Type: GrantFiled: November 27, 2013Date of Patent: June 21, 2016Assignee: INFINEON TECHNOLOGIES AGInventor: Steffen Thiele
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Publication number: 20160164279Abstract: Circuits, switches with over-current protection and methods for measuring a current are described herein. A circuit configured to provide a current from a supply voltage to a load includes a first transistor, a second transistor, and a detecting circuit. The first transistor has a larger active area than the second transistor. The detecting circuit is configured to detect a current through the second transistor. A same voltage is applied between a control terminal of the first transistor and a first controlled terminal of the first transistor and is applied between a control terminal of the second transistor and a first controlled terminal of the second transistor. The detecting circuit is coupled to the second controlled terminal of the second transistor and is coupled to the supply voltage.Type: ApplicationFiled: December 9, 2014Publication date: June 9, 2016Inventors: Michael Asam, Andreas Meiser, Steffen Thiele
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Patent number: 9291374Abstract: An adsorber structure for a heat pump, having at least one pipe, through which a heat-transfer fluid can flow, and an adsorption medium, wherein a working medium can be adsorbed and desorbed on the adsorption medium and the adsorption medium is in thermal connection with the pipe, wherein the adsorption medium is designed as at least one, in particular several, molded bodies, which is/are directly adjacent to a pipe wall of one of the pipes.Type: GrantFiled: January 21, 2014Date of Patent: March 22, 2016Assignee: MAHLE International GmbHInventors: Roland Burk, Hans-Heinrich Angermann, Thomas Schiehlen, Eberhard Zwittig, Steffen Thiele, Thomas Wolff, Holger Schroth, Stefan Felber, Steffen Brunner
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Publication number: 20160011232Abstract: A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.Type: ApplicationFiled: July 9, 2014Publication date: January 14, 2016Inventors: Carlos Marques Martins, Steffen Thiele, Aron Theil
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Publication number: 20150311196Abstract: An integrated semiconductor device is provided. According to an embodiment, the integrated semiconductor device includes a semiconductor body having a first surface with a normal direction defining a vertical direction, an opposite surface, a first area including a vertical power field-effect transistor structure, a second area including a three-terminal step-down level-shifter, and a third area including a three-terminal step-up level-shifter. A terminal of the vertical power field-effect transistor structure is electrically connected with one of the three-terminal step-down level-shifter and the three-terminal step-up level-shifter.Type: ApplicationFiled: July 9, 2015Publication date: October 29, 2015Inventors: Franz Hirler, Andreas Meiser, Steffen Thiele
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Patent number: 9111764Abstract: A bridge circuit is provided. The bridge circuit includes a first integrated semiconductor device having a high-side switch, a second integrated semiconductor device having a low-side switch electrically connected with the high-side switch, a first level-shifter electrically connected with the high-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device, and a second level-shifter electrically connected with the low-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device. Further, an integrated semiconductor device is provided.Type: GrantFiled: July 13, 2012Date of Patent: August 18, 2015Assignee: INFINEON TECHNOLOGIES AGInventors: Franz Hirler, Andreas Meiser, Steffen Thiele
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Patent number: 9087829Abstract: A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another.Type: GrantFiled: August 5, 2011Date of Patent: July 21, 2015Assignee: Infineon Technologies AGInventors: Stefan Macheiner, Andreas Peter Meiser, Steffen Thiele
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Patent number: 9082773Abstract: An integrated circuit including a semiconductor device has a power component including a plurality of trenches in a cell array, the plurality of trenches running in a first direction, and a sensor component integrated into the cell array of the power component and including a sensor cell having an area which is smaller than an area of the cell array of the power component. The integrated circuit further includes isolation trenches disposed between the sensor component and the power component, an insulating material being disposed in the isolation trenches. The isolation trenches run in a second direction that is different from the first direction.Type: GrantFiled: January 30, 2013Date of Patent: July 14, 2015Assignee: Infineon Technologies AGInventors: Andreas Meiser, Markus Zundel, Steffen Thiele