Patents by Inventor Steffen Wirth

Steffen Wirth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11717217
    Abstract: A computer-implemented method for indicating a long-term stress level of a person by means of a data processing unit, including the steps of acquiring stressor data having a set of stressor data items; analyzing stressor data values of the stressor data items by means of an artificial neural network to generate data representing a stress level, wherein the artificial neural network (ANN) is trained to provide output representing the stress level based on the stressor data values and an indication of previous stress state; and signaling the stress level.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 8, 2023
    Inventor: Steffen Wirth
  • Publication number: 20200305791
    Abstract: A computer-implemented method for indicating a long-term stress level of a person by means of a data processing unit, including the steps of acquiring stressor data having a set of stressor data items; analyzing stressor data values of the stressor data items by means of an artificial neural network to generate data representing a stress level, wherein the artificial neural network (ANN) is trained to provide output representing the stress level based on the stressor data values and an indication of previous stress state; and signaling the stress level.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 1, 2020
    Inventor: Steffen Wirth
  • Publication number: 20130076383
    Abstract: A method for testing an integrated circuit and an integrated circuit. The integrated circuit has an internal testing structure which may be accessed via an internal test access port and a control bus which is conducted to the outside via control ports, it being possible to switch over between a running mode and a test mode so that, in the test mode, the test access port is accessed via the control ports and the control bus, thus testing the integrated circuit.
    Type: Application
    Filed: February 7, 2011
    Publication date: March 28, 2013
    Inventors: Peter Poinstingl, Christoph Knaupp, Helmut Randoll, Ralf Kraemer, Thomas Wieja, Steffen Wirth, Stefan Doehren, Thomas Braun