Abstract: A data processing system executes two instruction sequences in an order determined in advance. Each sequence is stored in a separate memory. Data information used in the second sequence is not guaranteed to be independent of data information used in the first sequence. Increased data handling capacity is achieved in the following manner: both sequences are initially executed in parallel. An address included in a read instruction associated with the second sequence is intermediately stored in an auxiliary memory if it has not been previously selected in conjunction with a write instruction of the second sequence. The intermediately stored address is compared with the write addresses of the first sequence and execution of the second sequence is restarted upon detection of a match.

Abstract: A data processing system which executes two instruction sequences in an order determined in advance. With the aid of instructions, a main memory common to both sequences is activated for data information reading/writing. Increased data handling capacity is achieved in the following manner: both sequences are executed in parallel to start with. During execution of the first sequence, the main memory is prevented from being activated for writing due to the second sequence write instructions. A write address and data information included in a write instruction associated with the second sequence are intermediately stored. The intermediately stored write address is compared with the read addresses of the second sequence, and data information is prevented from being read from the main memory in response to an identity of the addresses, the intermediately stored data information being read instead.

Abstract: A method and apparatus for determining what program shall utilize a rapid access memory in a computer working with a plurality of programs and having a conventional slow access (NM) memory and a rapid access memory (CM), characterized in that during a test period there is registered for each program the number of instructions in the program requiring access to the memory, this number being divided by the whole memory space required by a program, the quotients formed after each other in this way being compared with each other and for the program with the highest quotient the memory content is transferred from the slow access memory to the rapid access memory. For each program there is registered with the aid of a counter (RF) the number of instructions requiring access to the slow access memory (NM). This number is divided with the aid of a measuring circuit (R1, R2, JR, KB) by the entire memory space for the respective program noted in a space memory (SM).