Abstract: A controller of a processor core may select telemetry data generated by a plurality of sensors of the processor core at a first time interval of a plurality of time intervals. The controller may transform the telemetry data based at least in part on a model. The controller may detect a change at the first time interval based on the transformed telemetry data. The controller may determine an event based on the change. The controller may initiate an action during the first time interval based on the event.

Abstract: The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.

Abstract: The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.

Abstract: The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized.

Abstract: The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized.

Abstract: The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.

Abstract: The invention is a digital sounder module and its method for detection. The digital sounder module includes a sonar carrier wave producing means, a band-pass filter, a pre-amplifier for providing a high sensitivity and extending a wide dynamic range, and an analog-to-digital converter for providing a digital implementation of a superheterodyne detector and producing an intermediate frequency. The digital sounder module also includes a programmable logic device for controlling a gain of the pre-amplifier and for digitally filtering the intermediate frequency and a microprocessor. The method implemented by the controlled per-amplifier gain processes the return echo signal by controlled ramp up of the gain over time to compensate for the change in signal strength in proportion to the length of the return path.

Abstract: The invention is a digital sounder module and its method for detection. The digital sounder module includes a sonar carrier wave producing means, a band-pass filter, a pre-amplifier for providing a high sensitivity and extending a wide dynamic range, and an analog-to-digital converter for providing a digital implementation of a superheterodyne detector and producing an intermediate frequency. The digital sounder module also includes a programmable logic device for controlling a gain of the pre-amplifier and for digitally filtering the intermediate frequency and a microprocessor. The method implemented by the controlled per-amplifier gain processes the return echo signal by controlled ramp up of the gain over time to compensate for the change in signal strength in proportion to the length of the return path.

Abstract: The invention is a digital sounder module and its method for detection. The digital sounder module includes a sonar carrier wave producing means, a band-pass filter, a pre-amplifier for providing a high sensitivity and extending a wide dynamic range, and an analog-to-digital converter for providing a digital implementation of a superheterodyne detector and producing an intermediate frequency. The digital sounder module also includes a programmable logic device for controlling a gain of the pre-amplifier and for digitally filtering the intermediate frequency and a microprocessor. The method implemented by the controlled per-amplifier gain processes the return echo signal by controlled ramp up of the gain over time to compensate for the change in signal strength in proportion to the length of the return path.

Abstract: The invention is a digital sounder module and its method for detection. The digital sounder module includes a sonar carrier wave producing means, a band-pass filter, a pre-amplifier for providing a high sensitivity and extending a wide dynamic range, and an analog-to-digital converter for providing a digital implementation of a superheterodyne detector and producing an intermediate frequency. The digital sounder module also includes a programmable logic device for controlling a gain of the pre-amplifier and for digitally filtering the intermediate frequency and a microprocessor. The method implemented by the controlled per-amplifier gain processes the return echo signal by controlled ramp up of the gain over time to compensate for the change in signal strength in proportion to the length of the return path.