Abstract: An encoder device includes an array of detectors that are operable to detect a flux and to generate currents in response to the detection; multiple current lines for conducting currents; a set of switches coupled between the array of detectors and the multiple current lines such that an output of each of the array of detectors is routed to none or one of the multiple current lines; and a controller operable to configure the set of switches.

Abstract: A current sense amplifier sensing current through a main switch of a converter. The amplifier includes first and second switch devices, an amplifier control circuit, a bias circuit, a current generator circuit, and a sense circuit. The main switch is coupled to an input, phase and control nodes. The first and second switch devices are smaller matching versions of the main switch and are both coupled to the main switch and form first and second nodes. The bias circuit is coupled between second and fourth nodes and the amplifier control circuit is coupled between first and third nodes. The current generator develops a first current through the amplifier control circuit and a second current through the bias circuit. The sense circuit has a current path coupled to the first node and is controlled by the third node to develop a sense voltage indicative of current through the main switch.

Abstract: A system and method for controlling a conversion frequency of a hysteretic mode voltage converter. A digital control loop comprises a timing measure unit having a first input coupled to a reference clock and a second input coupled to a clock based on a switching of the switching of the converter, and an on time adjust unit coupled to the timing measure unit. The timing measure unit counts a number of clock ticks of a clock signal provided by the clock occurring during a period of time specified by a number of clock ticks of a reference clock signal provided by the reference clock. The on time adjust unit adjusts an on time control signal based on the count of the number of clock ticks of the clock signal to alter a frequency of the switching.

Abstract: A current sense amplifier sensing current through a main switch of a converter. The amplifier includes first and second switch devices, an amplifier control circuit, a bias circuit, a current generator circuit, and a sense circuit. The main switch is coupled to an input, phase and control nodes. The first and second switch devices are smaller matching versions of the main switch and are both coupled to the main switch and form first and second nodes. The bias circuit is coupled between second and fourth nodes and the amplifier control circuit is coupled between first and third nodes. The current generator develops a first current through the amplifier control circuit and a second current through the bias circuit. The sense circuit has a current path coupled to the first node and is controlled by the third node to develop a sense voltage indicative of current through the main switch.

Abstract: A system and method for controlling a conversion frequency of a hysteretic mode voltage converter. A digital control loop comprises a timing measure unit having a first input coupled to a reference clock and a second input coupled to a clock based on a switching of the switching of the converter, and an on time adjust unit coupled to the timing measure unit. The timing measure unit counts a number of clock ticks of a clock signal provided by the clock occurring during a period of time specified by a number of clock ticks of a reference clock signal provided by the reference clock. The on time adjust unit adjusts an on time control signal based on the count of the number of clock ticks of the clock signal to alter a frequency of the switching.

Abstract: A signal-level compensating system consists of a voltage-follower stage, a sensor and a output signal compensator. The voltage-follower stage includes a signal input for receiving an input signal, a signal output, and at least one transistor coupled between the signal input and the signal output for providing an output signal responsive to the input signal. The sensor provides a control signal indicative of variations in at least one of the power supply voltage and transistor characteristics of the transistor. The output signal compensator is coupled to the signal output and provides a compensator output signal responsive to the control signal for reducing the impact of the variations on the voltage-follower output signal.

Abstract: A pull-down circuit uses an npn transistor operating at close to saturation and the collector/emitter voltage is used as the pull-down voltage. To keep this within strict limits the npn transistor is connected in circuit with other transistors and resistors as well as a current source that generates a current proportional to absolute temperature. By selecting the values of the resistors and transistor parameters the collector/emitter voltage may be kept stable within a small range over wide temperature variation.

Abstract: A bipolar drive circuit comprises a differential or single-ended current mirror with signal inputs and outputs connected via resistors to a low voltage supply, e.g. 1.5 volts. A signal output voltage swing is determined and stabilized by a compensation circuit comprising a transistor having a base supplied with a reference voltage, a collector coupled via a resistor to the low voltage supply, and an emitter coupled via a resistor to ground, and a current mirror having an input coupled to the collector of the transistor and a current mirror output coupled to each signal input. A plurality of current mirror circuits can be connected in cascade, and the signal output voltage swing of each current mirror circuit can be similarly determined. The arrangement facilitates providing a drive circuit with high frequency, low supply voltage, and low power operation without transistor saturation.

Abstract: A bias block switching unit is responsive to a power down control signal for switching between first and second states thereof, being operatively coupled to a reference voltage and coupled to a first supply voltage. A first switch is responsive to the power down control signal for switching between first and second states thereof. The first switch provides an output signal. A first switched constant current unit is coupled to the first switch and a first supply voltage. A first switched constant current unit has a first state for providing a constant current output and a second state for providing substantially no current. The first switched constant current unit is responsive to a bias signal for switching between first and second states thereof. The bias signal is outputted from the bias block switching unit. A first voltage follower receives an input signal, is operatively coupled to a second voltage supply and operatively coupled to the first switch.

Abstract: A switching circuitry and a switching method which reduces the influence of parasitic capacitance and provides improved signal performance at high frequencies. The circuitry may comprise a transistor having a source connected to an input node having an output resistance R2, and a drain is connected to the output node having an input resistance R3. The gate of the transistor is connected to a control node with output resistance R12 generating a control signal which opens or closes the transistor. By arranging that R1>>R2 (and assuming that R1≧R3), high frequency circuitry characteristics are dramatically improved, and the circuit provides high frequency voltage gain approaching unity and phase shift between the output and input voltages approaching zero to reduce signal degradation. Alternative arrangements may employ bipolar, FET, or MOS transistors or transistor pairs. The switching circuitry has numerous applications, e.g.

Abstract: The invention relates to a voltage reference source which is operable at a low voltage supply, e.g. 1.5V or lower, and allows for independent control of the magnitude and temperature dependence of the reference voltage. The source includes three transistors connected in parallel balanced with five resistors so as to provide the reference voltage in the form: Vr=m1Vbe+m2VT+Vbe, wherein Vr is the reference voltage, Vbe is a base-emitter voltage of a transistor, VT is a thermal voltage, and m1 and m2 are weight coefficients whose absolute and relative magnitudes can be varied. The sixth resistor is used for connection to a positive voltage. Corresponding method of forming the reference voltage is provided.

Abstract: A pull-down circuit uses an npn transistor operating at close to saturation and the collector/emitter voltage is used as the pull-down voltage. To keep this within strict limits the npn transistor is connected in circuit with other transistors and resistors as well as a current source that generates a current proportional to absolute temperature. By selecting the values of the resistors and transistor parameters the collector/emitter voltage may be kept stable within a small range over wide temperature variation.

Abstract: A bipolar drive circuit comprises a differential or single-ended current mirror with signal inputs and outputs connected via resistors to a low voltage supply, e.g. 1.5 volts. A signal output voltage swing is determined and stabilized by a compensation circuit comprising a transistor having a base supplied with a reference voltage, a collector coupled via a resistor to the low voltage supply, and an emitter coupled via a resistor to ground, and a current mirror having an input coupled to the collector of the transistor and a current mirror output coupled to each signal input. A plurality of current mirror circuits can be connected in cascade, and the signal output voltage swing of each current mirror circuit can be similarly determined. The arrangement facilitates providing a drive circuit with high frequency, low supply voltage, and low power operation without transistor saturation.

Abstract: The invention relates to a differential current mirror circuit with low or eliminated differential current offset. The circuit comprises first and second input transistors Q1i and Q2i whose physical layout is being matched and emitters connected together to a first reference voltage Vref1 through an input resistance means Ri; first and second output transistors Q1o and Q2o whose physical layout is being matched and emitters connected together to a second reference voltage Vref2 through an output resistance means Ro; collector and base of the first (second) input transistor Q1i (Q2i) being connected to the base of the first (second) output transistor Q1o (Q2o) and to a first (second) input current terminal to which a first (second) input current i1i (i2i) is being supplied; and collector of the first (second) output transistor Q1o (Q2o) being connected to a first (second) output current terminal generating first (second) output current i1o (i2o).

Abstract: A signal level shifting circuit comprises an emitter-follower transistor with a base supplied with an input signal, a collector coupled to a supply voltage, and an emitter coupled via a level shifter to a bias circuit, whereby a level shifted signal is produced at a junction point between the level shifter and the bias circuit. The level shifter comprises one or more diodes to provide a forward voltage drop providing a signal level shift, a PMOS transistor switch in parallel with the diode(s), and a control circuit responsive to the supply voltage for controlling the switch to bypass the diode(s), thereby providing a smaller level shift, when the supply voltage has a lower one of two possible values. The circuit can have a differential input and a differential output stage, and cascode-connected transistors for reducing voltages so that the circuit can be implemented using BCMOS technology.

Abstract: A signal voltage converter converts a 0V to −5V input signal to a +5V to 0V output signal using PMOS transistors for both pull-up and pull-down of the output. Bipolar transistor level shifters and PMOS current mirrors are used to control the pull-up and pull-down transistors in conjunction with a clamp circuit. Output signal transitions are matched for both transition directions to reduce signal timing distortion, and this can be further enhanced by an optional circuit for supplying a controlled current for the clamp circuit.